AD1836AS datasheet(14/18 Pages) AD

14 / 18 page

PRELIMINARY TECHNICAL DATA

REV. PrC

AD1836

–14–

AUXDATA1

ASDATA2/DAUXDATA

DATA TO EXT DAC

BCLK AND LRCLK FOR

EXT DAC COMES FROM

ADC BCLK, LRCLK.

MUST BE IN 12S MODE

ADC

SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO

RESET INTERNAL ADC COUNTER

ASDATA1

AUXDATA

12S FORMATTER

MUX

AUXLRCLK

2 AUX

CHANNELS

6-CH

DAC

6 MAIN

CHANNELS

DAC

SPORT

DSDATA1

DSDATA2

DSDATA3

LRCLK

BCLK

SPORT

SYNC

4 ADCS

AUXBCLK

AUXLRCLK

AUXDATA2

12S

DECODE

LRCLK

ABCLK

ASDATA1

ALRCLK

ABCLK

ASDATA1

DATA TO SHARC

INDICATES MUX POSITION FOR AUX-TDM MODE

MASTER/SLAVE MODE,

FROM ADC SPI PORT

FROM SHARC

FROM EXT A/D

DSDATA1

DSDATA2/AUXDATA1

DSDATA3/AUXDATA2

DLRCLK/AUXLRCLK

MCLK

12S

TIMING GEN

LRCLK BCLK

MUX

DBCLK/AUXBCLK

MUX

AUXBCLK

Figure 11. Extended TDM Mode Internal Flow Diagram

Table I. Pin Function Changes in AUX-Mode

Pin Name (I

2S/AUX-Mode)

2S-Mode

AUX-Mode

ASDATA1(O)

I2S Data Out, Internal ADC1

TDM Data Out, to SHARC

ASDATA2(O)/DAUXDATA(O)

2S Data Out, Internal ADC2

AUX–I

2S-Data Out (to Ext. DAC)

DSDATA1(I)

2S Data In, Internal DAC1

TDM Data In, from SHARC

DSDATA2(I)/AAUXDATA(I)

I2S Data In, Internal DAC2

AUX–I2S-Data in 1 (from Ext. ADC)

DSDATA3(I)/AAUXDATA2(I)

2S Data in Internal DAC3

AUX–I

2S-Data in 2 (from Ext. ADC)

ALRCLK(O)

LRCLK for Internal ADC1, 2

TDM Frame Sync Out, to SHARC

ABCLK(O)

BCLK for Internal ADC1, 2

TDM BCLK Out, to SHARC

DLRCLK(I)/AUXLRCLK(I/O)

LRCLK In/Out Internal DACs

AUX LRCLK IN/OUT, Driven by Ext. IRCLK

from ADC (in Slave Mode). In Master Mode,

Driven by Internal MCLK/512.

DBCLK(I)/AUXBCLK(I/O)

BCLK In/Out Internal DACs

AUX BCLK IN/OUT, Drive by Ext. BCLK

from ADC (in Slave Mode). In Master Mode,

Driven by Internal MCLK/8.

AD1836AS Datasheet(PDF) 14 Page - Analog Devices

AD1836AS Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL