PRELIMINARY TECHNICAL DATA

REV. PrC

AD1836

–17–

ADC Control Register 3

Function

Left

Left

Right

Right

Clock

Left Diff.

Right Diff.

MUX/PGA

MUX

MUX/PGA

MUX

Address

RD/WR

Reserved

Mode

I/P Select

I/P Select

Enable

I/P Select

Enable

I/P Select

15, 14, 13, 12

11

10, 9, 8

7, 6

5

4

3

2

1

0

1110

0

000

00 = 256

0 = Differential

0 = Differential

0 = Direct

0 = I/P 0

0 = Direct

0 = I/P 0

01 = 512

PGA Mode.

PGA Mode.

1 = MUX/

1 = I/P 1

1 = MUX/

1 = I/P 1

10 = 768

1 = PGA/MUX

1 = PGA/MUX

PGA

PGA

Mode (Single-

Mode (Single-

Ended Input)

Ended Input)

*When changing clock doubler bypass mode, other SPI bits that are written during the same SPI transaction may be lost. It is therefore recommended that a separate

transaction be used for setting CLKDBL Bypass Mode.

ADC Peak Level Data Registers

Peak Level Data (10 Bits)

Address

RD/WR

RSVD

6-Data Bits

4-Fixed Bits

15, 14, 13, 12

11

10

9..4

3..0

1000 = ADC0

1

0

000000 = 0.0 dBFS

0000

1001 = ADC1

000001 = –1.0 dBFS

1010 = ADC2

000010 = –2.0 dBFS

1011 = ADC3

000011 = –3.0 dBFS

The four LSBs are always zero.

.

.

.

111111 = –63 dBFS

AD1836

ADC2L

C1

1nF

C2

1nF

LEFT

INPUT #1

LEFT

INPUT #2

CAP1L

INPUT SELECT

250

PGA

–

+

–

+

250

CAP2L

GAIN SELECT

POWER-DOWN

NOTE

ADC2 SINGLE-ENDED MUX PGA INPUT MODE – LEFT CHANNEL ONLY SHOWN

CONTROL REGISTER 3 CONTENTS: 6 LSBS: SELECT INPUT #1: 11 1010

SELECT INPUT #2: 11 1111

Figure 12. Single-Ended MUX/PGA Mode

AD1836

ADC2L

C1

1nF

C2

1nF

LEFT + VE

INPUT

LEFT – VE

INPUT

CAP1L

250

–

+

250

+

CAP2L

GAIN SELECT

POWER-DOWN

NOTE

ADC2 DIFFERENTIAL PGA INPUT MODE – LEFT CHANNEL ONLY SHOWN

CONTROL REGISTER 3 CONTENTS: 6 LSBS: 00 1010

Figure 13. Differential Mode