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COP684FH Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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COP684FH Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 49 page  Timers (Continued) TIMER CONTROL FLAGS The control bits and their functions are summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture) TxPNDA Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled TxPNDB Timer Interrupt Pending Flag TxENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below: Mode TxC3 TxC2 TxC1 Description Interrupt A Source Interrupt B Source Timer Counts On 1 1 0 1 PWM: TxA Toggle Autoreload RA Autoreload RB t C 1 0 0 PWM: No TxA Toggle Autoreload RA Autoreload RB t C 2 0 0 0 External Event Counter Timer Underflow Pos. TxB Edge Pos. TxA Edge 0 0 1 External Event Counter Timer Underflow Pos. TxB Edge Pos. TxA Edge 3 0 1 0 Captures: Pos. TxA Edge Pos. TxB Edge t C TxA Pos. Edge or Timer TxB Pos. Edge Underflow 1 1 0 Captures: Pos. TxA Neg. TxB t C TxA Pos. Edge Edge or Timer Edge TxB Neg. Edge Underflow 0 1 1 Captures: Neg. TxA Neg. TxB t C TxA Neg. Edge Edge or Timer Edge TxB Neg. Edge Underflow 1 1 1 Captures: Neg. TxA Neg. TxB t C TxA Neg. Edge Edge or Timer Edge TxB Neg. Edge Underflow Power Save Modes The device offers the user two power save modes of opera- tion: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscil- lator circuitry and timer T0 are active but all other microcon- troller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered. HALT MODE The device can be placed in the HALT mode by writing a “1” to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The WATCH- DOG logic on the device is disabled during the HALT mode. However, the clock monitor circuitry if enabled remains ac- tive and will cause the WATCHDOG output pin (WDOUT) to go low. If the HALT mode is used and the user does not want to activate the WDOUT pin, the Clock Monitor should be dis- abled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the HALT mode, the power requirements of the device are minimal and the applied voltage (V CC) may be decreased to V r (Vr = 2.0V) without altering the state of the machine. The device supports three different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configura- DS012602-14 FIGURE 10. Timer in Input Capture Mode www.national.com 18 |
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