COP684FH datasheet(21/49 Pages) NSC

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Multi-Input Wakeup (Continued)

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT mode for clock option wakeup information.)

Note: There is always the possibility of an interrupt occurring during an in-

struction which is attempting to reset the GIE bit or any other interrupt

enable bit. If this occurs when a single cycle instruction is being used

to reset the interrupt enable bit, the interrupt enable bit will be reset but

an interrupt may still occur. This is because interrupt processing is

started at the same time as the interrupt bit is being reset. To avoid this

scenario, the user should always use a two, three, or four cycle instruc-

tion to reset interrupt enable bits.

USART

The device contains a full-duplex software programmable

USART. The USART (

Figure 12) consists of a transmit shift

isters, as follows: a transmit buffer register (TBUF), a re-

ceiver buffer register (RBUF), a USART control and status

(ENUR), a USART interrupt and clock source register

(ENUI), a prescaler select register (PSR) and baud (BAUD)

ceive functions; this register also determines the length of

the data frame (7, 8 or 9 bits), the value of the ninth bit in

transmission, and parity selection bits. The ENUR register

flags framming, data overrun and parity errors while the US-

ART is receiving.

Other functions of the ENUR register include saving the

ninth bit received in the data frame, enabling or disabling the

USART’s attention mode of operation and providing addi-

tional receiver/transmitter status information via RCVG and

XMTG bits. The determination of an internal or external clock

source is done by the ENUI register, as well as selecting the

number of stop bits and enabling or disabling transmit and

receive interrupts. A control flag in this register can also se-

lect the USART mode of operation: asynchronous or

synchronous.

DS012602-16

FIGURE 12. USART Block Diagram

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