MB9D560 datasheet(3/91 Pages) CYPRESS

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Document Number: 002-05679 Rev.*A

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MB9D560 Series

Main SRAM (TCRAM)

BTCM connection of Cortex-R5F



1 main SRAM as CPU 1 unit



Interleave with 2 ports of B0TCM and B1TCM

ECC support (SEC-DED)

BootROM

Size: 16K byte

Boot operation support

Serial writer program support

DMA controller (DMAC)

16 channels

Transfer mode



Block transfer, Burst transfer

Addressing mode



Fixed, increment

Priority between channels



Fixed, Dynamic, Round robin

Interrupt control (IRC)

Support normal interrupt (IRQ) and non-maskable interrupt

(NMI)

Normal interrupt (IRQ)



Use Interrupt Request (IRQ) of Cortex-R5F



512 channels



32 level for priority

Support low latency interrupt response from VIC port of

Cortex-R5F

Non-maskable interrupt (NMI)



Use fast interrupt request (FIQ) of Cortex-R5F



32 channels



16 level for priority

Support software interrupt generation

External interrupt (EXT-IRQ)

Input



Normal interrupt (IRQ): 8 input



Non-maskable interrupt (NMI): 1 input

Detection method



H level , L level , rise edge, fall edge, both edge

Inter-processor communications unit (IPCU)

Mailbox function



Data communication for CPU core communication by 8

Mailbox



Support of interrupt between CPU core

Exclusion access memory (EAM)

Small size memory to support exclusion control on exclusion

access instruction

Use for semaphore

Size: 48 byte

Bit-band unit (BBU)

The bit operation of specified register bit on Bit band area, it

is mapping 1 bit of bit band area to support bit band alias

area for 1 byte. The target of bit band access is specified

CRC

Output to register of CRC code according real time writing to

input register

Base timer

16-bit timer



Any of four PWM/PPG/reload/PWC timer functions can be

selected and used.



A 32-bit timer can be used in 2 channels of cascade mode

as reload/PWC timer.

16-bit free-run timer (FRT)

16 bit up/down counter (2 channels for motor control only)

32-bit free-run timer

32 bit up/down counter

16-bit input capture (ICU)

Input capture



16-bit capture register that detects rise edge, Fall edge,

both edge



Generate interrupt request after latch of counter number of

16 bit



Free-run timer with edge detection of pin input

32-bit input capture

Input capture



32-bit capture register that detects rise edge, fall edge,

both edge



Generate interrupt request after latch of counter number of

32 bit



Free-run timer with edge detection of pin input

LIN sync break/sync field relation is following.



Input capture ch.0

 Multi-function serial interface ch.0



Input capture ch.1

 Multi-function serial interface ch.1



Input capture ch.2

 Multi-function serial interface ch.2



Input capture ch.3

 Multi-function serial interface ch.3



Input capture ch.4

 Multi-function serial interface ch.4

16-bit output compare (OCU)

Output interrupt signal when compare with 16-bit free-run

timer

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