M59PW1282 datasheet(4/24 Pages) STMICROELECTRONICS

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M59PW1282

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SUMMARY DESCRIPTION

The M59PW1282 is a 128Mbit (8Mb x16), Mask-

ROM pinout compatible, non-volatile LightFlash™

memory, that can be read, erased and repro-

grammed. Read operations can be performed us-

ing a single low voltage (2.7 to 3.6V) supply.

Program and Erase operations require an addi-

tional VPP (11.4 to 12.6V) power supply. On pow-

er-up the memory defaults to its Read mode where

it can be read in the same way as a ROM or

EPROM.

The Mask-ROM compatibility is obtained using a

dual function Address/Voltage Supply pin (A22/

VPP). In Read mode the A22/VPP pin works as an

address pin; in Program or Erase mode it also

works as a voltage supply pin. At the beginning of

any program or erase operation, a specific proce-

dure (see Figure 4) must be performed to internal-

ly memorize the A22 value that will be used during

the program or erase operation.

The device is composed of two 64Mbit memories

stacked in a single package. Recommended oper-

ating conditions do not allow both memories to be

active at the same time. Address A22 selects the

memory to be enabled. The other memory is in

Standby mode.

The memory is divided into 64 uniform blocks that

can be erased independently so it is possible to

preserve valid data while old data is erased. Pro-

gram and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller (P/E.C.) simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents.

The M59PW1282 features an innovative com-

mand, Multiple Word Program, that is used to pro-

gram large streams of data. It greatly reduces the

total programming time when a large number of

Words are written to the memory at any one time.

Using this command the entire memory can be

programmed in 16s, compared to 72s using the

standard Word Program.

The end of a Program or Erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards. Chip Enable

and Output Enable signals control the bus opera-

tion of the memory. They allow simple connection

to most microprocessors, often without additional

logic.

The memory is offered in SO44 package and is

supplied with all the bits set to ’1’).

Figure 2. Logic Diagram

Table 1. Signal Names

AI07209

A0-A21

DQ0-DQ15

VCC

M59PW1282

VSS

A22/VPP

A0-A21

Address Inputs

A22/VPP

Address Input/Supply Voltage for

Program/Erase

DQ0-DQ15

Data Inputs/Outputs

Chip Enable

Output Enable

VCC

Supply Voltage read

VSS

Ground

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