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PC33889 Datasheet(PDF) 22 Page - Motorola, Inc |
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PC33889 Datasheet(HTML) 22 Page - Motorola, Inc |
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22 / 30 page ![]() PC33889 22 PC33889 7.2 Register description 7.2.1 MCR Register Control bits (1): Bit BATFAIL cannot be set by SPI. BATFAIL is set when Vsup falls below 3V. (2): Watchdog ON or OFF depends upon RCR register bit D3. (3): Before entering sleep mode, bit NOSTOP in RCR register must be previously set to 1. Status bits MCR D3D2D1D0 $000b W MCTR2 MCTR1 MCTR0 R BATFAIL VDDTEMP GFAIL WDRST Reset 0000 Reset condition POR, RESET POR, RESET POR, RESET Table 7-2. MCTR2 MCTR1 MCTR0 SBC mode Description 0 0 0 Enter/leave debug mode To enter debug mode, SBC must be in Normal or Standby mode and BATFAIL(1) must be still at 1. To leave debug mode, BATFAIL must be at 0. 00 1 Normal 0 1 0 Standby 0 1 1 Stop, watchdog off (2) 0 1 1 Stop, watchdog on (2) 10 0 Sleep (3) 10 1 Normal No watchdog running, debug mode 1 1 0 Standby 11 1 Stop Status bit Description GFAIL Logic OR of CAN failure, HS1 failure, V2LOW BATFAIL Battery fail flag (Vsup<3V) VDDTEMP Temperature pre-warning on VDD (latched) WDRST Watchdog reset occurred Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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