GND

SAMPLING

CAPACITOR

SW1

-

+

CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

V

/2

DD

V

IN

GND

SAMPLING

CAPACITOR

SW1

-

+

CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

V

/2

DD

SW2

V

IN

17

ADCS7476, ADCS7477, ADCS7478

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SNAS192G – APRIL 2003 – REVISED MAY 2016

Product Folder Links: ADCS7476 ADCS7477 ADCS7478

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7.4 Device Functional Modes

Figure 25 shows the device in hold mode where the switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the

comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital

representation of the analog input voltage. The device moves from hold mode to track mode (Figure 26) on the

13th rising edge of SCLK.

Figure 25. ADCS747x in Hold Mode

Figure 26. ADCS747x in Track Mode

7.4.1 Transfer Function

The output format of ADCS747x is straight binary. Code transitions occur midway between successive integer

shown in Figure 27, while the ideal transfer characteristic for the ADCS7478 is shown in Figure 28.