ADCS7477 datasheet(10/33 Pages) TI1

10 / 33 page

ADCS7476, ADCS7477, ADCS7478

SNAS192G – APRIL 2003 – REVISED MAY 2016

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Product Folder Links: ADCS7476 ADCS7477 ADCS7478

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Timing Requirements (continued)

–40°C

≤ TA ≤ 85°C, VDD = 2.7 V to 5.25 V, and fSCLK = 20 MHz (unless otherwise noted)

(1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

(4)

Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V or 2 V.

(5)

t8 is derived from the time taken by the outputs to change by 0.5 V with the loading circuit (Figure 1). The measured number is then

adjusted to remove the effects of charging or discharging the 25-pF capacitor. This means t8 is the true bus relinquish time, independent

of the bus loading.

Data access time after SCLK falling edge(4)

VDD = 2.7 V to 3.6 V

VDD = 4.75 V to 5.25 V

SCLK low pulse width

0.4 × tSCLK

SCLK high pulse width

0.4 × tSCLK

SCLK to data valid hold time

VDD = 2.7 V to 3.6 V

VDD = 4.75 V to 5.25 V

SCLK falling edge to SDATA high

impedance (5)

VDD = 2.7 V to 3.6 V

VDD = 4.75 V to 5.25 V

tPOWER-UP

Power-up time from full power down

TA = 25°C

µs

Figure 1. Timing Test Circuit

Figure 2. ADCS7476 Serial Interface Timing Diagram

ADCS7477 Datasheet(PDF) 10 Page - Texas Instruments