ADCS7477 datasheet(9/33 Pages) TI1

9 / 33 page

ADCS7476, ADCS7477, ADCS7478

www.ti.com

SNAS192G – APRIL 2003 – REVISED MAY 2016

Product Folder Links: ADCS7476 ADCS7477 ADCS7478

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Electrical Characteristics – ADCS7478 (continued)

TA = 25°C, VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, and fSAMPLE = 1 MSPS (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power consumption,

normal mode (operational)

VDD = 5 V,

fSAMPLE = 1 MSPS

TA = 25°C

–40°C

≤ TA ≤ 85°C

17.5

VDD = 3 V,

fSAMPLE = 1 MSPS

TA = 25°C

–40°C

≤ TA ≤ 85°C

4.8

Power consumption,

shutdown mode

VDD = 5 V, SCLK Off

2.5

µW

VDD = 3 V, SCLK Off

1.5

ANALOG INPUT CHARACTERISTICS

VIN

Input range

0 to VDD

IDCL

DC leakage current

–40°C

≤ TA ≤ 85°C

±1

µA

CINA

Analog input capacitance

DIGITAL INPUT CHARACTERISTICS

VIH

Input high voltage

–40°C

≤ TA ≤ 85°C

2.4

VIL

Input low voltage

VDD = 5 V, –40°C ≤ TA ≤ 85°C

0.8

VDD = 3 V, –40°C ≤ TA ≤ 85°C

0.4

IIN

Digital input current

VIN = 0 V or VDD

TA = 25°C

±10

–40°C

≤ TA ≤ 85°C

±1

µA

CIND

Input capacitance

TA = 25°C

–40°C

≤ TA ≤ 85°C

DIGITAL OUTPUT CHARACTERISTICS

VOH

Output high voltage

ISOURCE = 200 µA, VDD = 2.7 V to 5.25 V,

–40°C

≤ TA ≤ 85°C

VDD − 0.2

VOL

Output low voltage

ISINK = 200 µA, –40°C ≤ TA ≤ 85°C

0.4

IOL

TRI-STATE leakage current

–40°C

≤ TA ≤ 85°C

±10

µA

COUT

TRI-STATE output capacitance

Output coding

Straight (natural) binary

AC ELECTRICAL CHARACTERISTICS

fSCLK

Clock frequency

–40°C

≤ TA ≤ 85°C

MHz

SCLK duty cycle

–40°C

≤ TA ≤ 85°C

40%

60%

tTH

Track or hold acquisition time

–40°C

≤ TA ≤ 85°C

400

fRATE

Throughput rate

–40°C

≤ TA ≤ 85°C (see Application Information)

MSPS

tAD

Aperture delay

tAJ

Aperture jitter

(1)

All input signals are specified as tr = tf = 5 ns (10% to 90% VDD) and timed from 1.6 V.

(2)

Minimum quiet time required between bus relinquish and start of next conversion.

(3)

Measured with the load circuit (Figure 1), and defined as the time taken by the output to cross 1 V.

6.8 Timing Requirements

–40°C

≤ TA ≤ 85°C, VDD = 2.7 V to 5.25 V, and fSCLK = 20 MHz (unless otherwise noted)

(1)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

tCONVERT

TA = 25°C

16 × tSCLK

tQUIET

Quiet time(2)

Minimum CS pulse width

CS to SCLK setup time

Delay from CS until SDATA TRI-STATE

disabled (3)

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