ADS5545 datasheet(39/59 Pages) TI1

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CLKP

CLKM

DifferentialSine-Wave

orPECL orLVDS

ClockInput

ADS5545

0.1 F

CLKP

CLKM

CMOSClockInput

ADS5545

0.1 F

Input Clock Buffer Gain

ADS5545

SLWS180C – NOVEMBER 2005 – REVISED MAY 2007

APPLICATION INFORMATION (continued)

For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to

common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with

0.1-

µF capacitors, as in Figure 51.

Figure 51. Differential Clock Driving Circuit

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with

a 0.1-

µF capacitor, as in Figure 52.

Figure 52. Single-Ended Clock Driving Circuit

For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode

noise. For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass

filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a

non-50% duty cycle clock input. Figure 33 shows the performance variation of the ADC versus clock duty cycle

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is

increased. Therefore, using a large amplitude clock is recommended. In addition, the clock buffer has a

programmable gain option to amplify the input clock. There are 5 gain settings, with Gain 4 being the maximum

gain and Gain 0 the minimum gain setting. The default gain is Gain 1. The clock buffer gain can be set by

programming the register bits <CLKIN GAIN> (Table 14).

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