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AM5K2E02 Datasheet(PDF) 7 Page - Texas Instruments |
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AM5K2E02 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 252 page  AM5K2E04, AM5K2E02 www.ti.com SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (August 2014) to Revision D Page • Added Top Navigation links to front page of the document ..................................................................... 1 • Changed Product Status to Production Data ..................................................................................... 1 • Changed Mission Critical Systems to Avionics and Defense in Section 1.2 .................................................. 2 • Changed mission critical to avionics and defense in first paragraph of Section 3.2.1 ...................................... 2 • Changed Product Status to PD and changed footnote (3) in Table 3-1 ....................................................... 8 • Changed second list item under Software Development Tools in Section 3.2.1 ........................................... 10 • Added Related Links, Community Resources, Trademarks, Electrostatic Discharge Caution, and Glossary sections to Section 3 ................................................................................................................ 13 • Added Figure 4-1 .................................................................................................................... 14 • Changed DDR3A to DDR3 in Table 4-1 ......................................................................................... 16 • Changed All instances of DDR3A to DDR3 in Table 5-2 ...................................................................... 25 • Changed Supply DDR3AREFSSTL to DDR3REFSSTL in Table 5-3 ........................................................ 38 • Changed the DVDD15 Volts and Supply Description in Table 5-3 ........................................................... 38 • Changed Start Address for PCIe1SerDes Config to 00 0232 6000, End Address for USB 0 MMR CFG to 00 026F FFFF, and all instances of DDR3A to DDR3 in Table 6-1 .............................................................. 55 • Changed CPT_DDR3A to CPT_DDR3 in Table 6-6 ............................................................................ 66 • Changed DDR3A to DDR3 in Event No. 388 Name and Description in Table 6-22 ....................................... 78 • Changed DDR3A to DDR3 in Section 6.4 ...................................................................................... 104 • Changed DDR3A to DDR3 in Section 7 ........................................................................................ 114 • Changed DDR3A to DDR3 in Figure 7-3 ....................................................................................... 117 • Changed DDR3A to DDR3 in Figure 7-6 ....................................................................................... 122 • Added EMIF and NAND to Description in Table 8-2 .......................................................................... 131 • Changed DDR3A to DDR3 in Section 8.1.4 .................................................................................... 147 • Changed DDR3APLLCTL0 and DDR3APLLCTL1 to DDR3PLLCTL0 and DDR3PLLCTL1 in Table 8-26 ............ 149 • Changed AVSIFSEL Description value 11 to Reserved in Table 8-27 ..................................................... 153 • Changed ARMENDIAN_CFG4_0 Default Value to 0x00023A00 in Table 8-42 ........................................... 164 • Changed ARMENDIAN_CFG5_1 Default Value to 0x00000006 in Table 8-44 ........................................... 165 • Changed DDR3AVREFSSTL to DDR3VREFSSTL and DDR3A to DDR3 in Section 9.1 ................................ 175 • Changed MIN, NOM, and MAX values for CVDD Initial and CVDD1; changed DVDD15 to DDR3 I/O voltage and added values; changed DDR3A to DDR3 and DDR3AVREFSSTL to DDR3VREFSSTL; changed DSP to SOC in footnote (4) in Section 9.2 ........................................................................................................ 176 • Changed DDR3A to DDR3 in Section 9.3 ...................................................................................... 177 • Changed DDR3A to DDR3 and changed DVDD15 to DDR3 memory I/O voltage and DDR3 (1.5/1.35 V) I/O Buffer Type in Table 9-1 .......................................................................................................... 178 • Changed DDR3A to DDR3 and added 1.35 V to Voltage for DVDD15 in Table 10-1 .................................... 179 • Changed EMIF(DDR3A) to EMIF(DDR3) in Table 10-6 ...................................................................... 187 • Changed DDR3A EMIF to DDR3 EMIF in Table 10-7 ........................................................................ 188 • Changed DDR3A in Section 10.4.3 ............................................................................................. 195 • Changed DDR3A in Section 10.5 ................................................................................................ 198 • Changed Figure 10-7 .............................................................................................................. 199 • Deleted second sentence from Section 10.5.1.1 .............................................................................. 200 • Changed DDR3A to DDR3 in Table 10-13 ..................................................................................... 201 • Changed Address Range 00 0231 0128 to Reserved in Table 10-15 ...................................................... 202 • Changed OUTPUT DIVIDE Field Description in Table 10-16 ............................................................... 203 • Changed MAX value for tj(CORECLKN) and tj(CORECLKP) in Table 10-27 ............................................. 209 • Changed Figure 10-26 ............................................................................................................ 214 • Changed PAPLL Field Description in Table 10-32 ............................................................................ 215 • Changed MAX value for tc(NETCPCLKN) and tc(NETCPCLKP) in Table 10-33 ......................................... 215 • Changed DDR3A Memory Controller to DDR3 Memory Controller in Section 10.8 ...................................... 216 • Changed MIN and MAX values for tc(CEL) in Table 10-56 .................................................................. 236 • Changed DDR3A to DDR3 in Table 10-62 ..................................................................................... 244 Copyright © 2012–2015, Texas Instruments Incorporated Revision History 7 Submit Documentation Feedback Product Folder Links: AM5K2E04 AM5K2E02 |
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