AM5K2E02 datasheet(16/252 Pages) TI1

16 / 252 page

AM5K2E04, AM5K2E02

SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015

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4.1

Features

The key features of the Quad Core ARM CorePac are as follows:

•

One or more Cortex-A15 processors, each containing:

–

Cortex-A15 processor revision R2P4.

–

ARM architecture version 7 ISA.

–

Multi-issue, out-of-order, superscalar pipeline.

–

L1 and L2 instruction and data cache of 32KB, 2-way, 16 word line with 128-bit interface.

–

Integrated L2 cache of 4MB, 16-way, 16-word line, 128-bit interface to L1 along with ECC/parity.

–

Includes the NEON media coprocessor (NEON™), which implements the advanced SIMDv2 media

processing architecture and the VFPv4 Vector Floating Point architecture.

–

The external interface uses the AXI protocol configured to 128-bit data width.

–

Includes the System Trace Macrocell (STM) support for non-invasive debugging.

–

Implements the ARMv7 debug with watchpoint and breakpoint registers and 32-bit advanced

peripheral bus (APB) slave interface to CoreSight™ debug systems.

•

Interrupt controller

–

Supports up to 480 interrupt requests

–

An integrated Global Time Base Counter (clocked by the SYSCLK divided by 6)

•

Emulation/debug

–

Compatible with CoreSight™ architecture

4.2

System Integration

The ARM CorePac integrates the following group of submodules.

•

Cortex-A15 Processors: Provides a high processing capability, including the NEON™ technology for

mobile multimedia acceleration. The Cortex-A15 communicates with the rest of the ARM CorePac

through an AXI bus with an AXI2VBUSM bridge and receives interrupts from the ARM CorePac

interrupt controller (ARM INTC).

•

Interrupt Controller: Handles interrupts from modules outside of the ARM CorePac (for details, see

Section 4.3.3).

•

Clock Divider: Provides the required divided clocks to the internal modules of the ARM CorePac and

has a clock input from the Main PLL.

•

In-Circuit Emulator: Fully compatible with CoreSight™ architecture and enables debugging

capabilities.

4.3

ARM Cortex-A15 Processor

4.3.1

Overview

The ARM Cortex-A15 processor incorporates the technologies available in the ARM7™ architecture.

These technologies include NEON™ for media and signal processing and Jazelle™ RCT for acceleration

of real-time compilers, Thumb®-2 technology for code density, and the VFPv4 floating point architecture.

For details, see the ARM Cortex-A15 Processor Technical Reference Manual.

4.3.2

Features

Table 4-1 shows the features supported by the Cortex-A15 processor core.

Table 4-1. Cortex-A15 Processor Core Supported Features

FEATURES

DESCRIPTION

ARM version 7-A ISA

Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and

media extensions

Backward compatible with previous ARM ISA versions

ARM CorePac

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