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AM1707 Datasheet(PDF) 70 Page - Texas Instruments

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Part # AM1707
Description  AM1707 ARM짰 Microprocessor
PDF  200 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM1707 Datasheet(HTML) 70 Page - Texas Instruments

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AM1707
SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014
www.ti.com
Table 6-22. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3)
No.
PARAMETER
MIN
NOM
MAX
UNIT
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 3
(TA)*E
(TA)*E + 3
ns
READS
(RS+RST+RH)*E
(RS+RST+RH)*E
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E
ns
- 3
+ 3
3
tc(EMRCYCLE)
(RS+RST+RH+E (RS+RST+RH+EWC (RS+RST+RH+E
EMIF read cycle time (EW = 1)
ns
WC)*E - 3
)*E
WC)*E + 3
Output setup time, EMA_CE[5:2] low to
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMA_OE low (SS = 0)
4
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to
-3
0
+3
ns
EMA_OE low (SS = 1)
Output hold time, EMA_OE high to
(RH)*E - 3
(RH)*E
(RH)*E + 3
ns
EMA_CE[5:2] high (SS = 0)
5
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to
-3
0
+3
ns
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
6
tsu(EMBAV-EMOEL)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMA_OE low
Output hold time, EMA_OE high to
7
th(EMOEH-EMBAIV)
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
8
tsu(EMBAV-EMOEL)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
EMA_OE low
Output hold time, EMA_OE high to
9
th(EMOEH-EMAIV)
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_A[13:0] invalid
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
10
tw(EMOEL)
(RST+EWC)*E+
EMA_OE active low width (EW = 1)
(RST+EWC)*E-3
(RST+EWC)*E
ns
3
td(EMWAITH-
Delay time from EMA_WAIT deasserted to
11
3E-3
4E
4E+3
ns
EMOEH)
EMA_OE high
WRITES
(WS+WST+WH)*
(WS+WST+WH)*
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E
ns
E-3
E+3
15
tc(EMWCYCLE)
(WS+WST+WH+E
(WS+WST+WH+EW (WS+WST+WH+
EMIF write cycle time (EW = 1)
ns
WC)*E - 3
C)*E
EWC)*E + 3
Output setup time, EMA_CE[5:2] low to
(WS)*E - 3
(WS)*E
(WS)*E + 3
ns
EMA_WE low (SS = 0)
16
tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to
-3
0
+3
ns
EMA_WE low (SS = 1)
Output hold time, EMA_WE high to
(WH)*E-3
(WH)*E
(WH)*E+3
ns
EMA_CE[5:2] high (SS = 0)
17
th(EMWEH-EMCEH)
Output hold time, EMA_WE high to
-3
0
+3
ns
EMA_CE[5:2] high (SS = 1)
tsu(EMDQMV-
Output setup time, EMA_BA[1:0] valid to
18
(WS)*E-3
(WS)*E
(WS)*E+3
ns
EMWEL)
EMA_WE low
th(EMWEH-
Output hold time, EMA_WE high to
19
(WH)*E-3
(WH)*E
(WH)*E+3
ns
EMDQMIV)
EMA_BA[1:0] invalid
tsu(EMBAV-
Output setup time, EMA_BA[1:0] valid to
20
(WS)*E-3
(WS)*E
(WS)*E+3
ns
EMWEL)
EMA_WE low
Output hold time, EMA_WE high to
21
th(EMWEH-EMBAIV)
(WH)*E-3
(WH)*E
(WH)*E+3
ns
EMA_BA[1:0] invalid
(1)
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2)
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3)
EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
70
Peripheral Information and Electrical Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
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