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DP83256VF Datasheet(PDF) 47 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83256VF
Description  PLAYERa??Device (FDDI Physical Layer Controller)
PDF  144 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83256VF Datasheet(HTML) 47 Page - National Semiconductor (TI)

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50 Registers (Continued)
54 INTERRUPT CONDITION MASK REGISTER (ICMR)
The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt
The Interrupt pin will be asserted (ie EINT e GND) when one or more bits within the Interrupt Condition Register (ICR) are set
to 1 and the corresponding mask bits in this register are also set to 1
This register is cleared (ie set to 0) and all interrupts are initially masked during the reset process
ACCESS RULES
ADDRESS
READ
WRITE
03h
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
UDIM
RCBM
RCAM
LEMTM
CWIM
CCRM
CPEM
DPEM
Bit
Symbol
Description
D0
DPEM
PHY
REQUEST
DATA PARITY ERROR MASK
The mask bit for the PHY
Request Data Parity Error bit
(DPE) of the Interrupt Condition Register (ICR)
D1
CPEM
Control Bus DATA PARITY ERROR MASK
The mask bit for the Control Bus Data Parity Error bit (CPE) of the
Interrupt Condition Register (ICR)
D2
CCRM
Control Bus WRITE COMMAND REJECT MASK
The mask bit for the Control Bus Write Command Reject bit
(CCR) of the Interrupt Condition Register (ICR)
D3
CWIM
CONDITIONAL WRITE INHIBIT MASK
The mask bit for the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR)
D4
LEMTM
LINK ERROR MONITOR THRESHOLD MASK
The mask bit for the Link Error Monitor Threshold bit (LEMT) of
the Interrupt Condition Register (ICR)
D5
RCAM
RECEIVE CONDITION A MASK
The mask bit for the Receive Condition A bit (RCA) of the Interrupt Condition
Register (ICR)
D6
RCBM
RECEIVE CONDITION B MASK
The mask bit for the Receive Condition B bit (RCB) of the Interrupt Condition
Register (ICR)
D7
UDIM
USER DEFINABLE INTERRUPT MASK
The mask bit for the User Definable Interrupt bit (UDI) of the Interrupt
Condition Register (ICR)
47



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