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DP83256VF Datasheet(PDF) 62 Page - National Semiconductor (TI) |
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DP83256VF Datasheet(HTML) 62 Page - National Semiconductor (TI) |
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62 / 144 page ![]() 50 Registers (Continued) 518 STATE THRESHOLD REGISTER (STR) The State Threshold Register contains the start value for the State Timer This timer is used in conjunction with the State Prescale Timer to count the Line State duration The State Timer will decrement every 80 ns if the State Prescale Timer is zero and the current Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect The State Timer takes ((SPTRa1) x STR a SPTR) x 80 ns to reach zero during a continuous line state condition The threshold values for the State Timer and State Prescale Timer are simultaneously loaded into both counters if one of the following conditions is true 1 Both the State Timer and State Prescale Timer reach zero and the current Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect or 2 A line state change occurs and the new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect or 3 The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle In addition the value of the State Prescale Threshold Register is loaded into the State Prescale Counter if the State Prescale Timer reaches zero The State Timer and State Prescale Timer will reset by reloading the threshold values if a Line State change occurs and the new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect On detection of ALS NLS or LSU the timer will not decrement ACCESS RULES ADDRESS READ WRITE 11h Always Always D7 D6 D5 D4 D3 D2 D1 D0 RES ST6 ST5 ST4 ST3 ST2 ST1 ST0 Bit Symbol Description D0-D6 ST0-ST6 STATE THRESHOLD BITk0-6l Start value for the State Timer ST0 is the Least Significant Bit (LSB) D7 RES RESERVED Reserved for future use Note Users are discouraged from using this bit Write data is ignored since the reserved bit is permanently set to 0 62 |
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