DP83256VF datasheet(9/144 Pages) NSC

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30 Functional Description (Continued)

32 RECEIVER BLOCK

During normal operation the Receiver Block accepts serial

data input at the rate of 125 Mbps from the Clock Recovery

Module During the Internal Loopback mode of operation

the Receiver Block accepts input data from the Transmitter

Block

The Receiver Block performs the following operations

Optionally converts the incoming data stream from NRZI

to NRZ

Decodes the data from 5B to 4B coding

Converts the serial bit stream into the National byte-wide

code

Compensates for the differences between the upstream

station clock and the local clock

Decodes Line States

Detects link errors

Presents data symbol pairs to the Configuration Switch

Block

The Receiver Block consists of the following functional

blocks

NRZI to NRZ Decoder

Shift Register

Framing Logic

Symbol Decoder

Line State Detector

Elasticity Buffer

Link Error Detector

See

Figure 3-2

NRZI TO NRZ DECODER

The NRZI to NRZ Decoder converts Non-Return-To-Zero-

Invert-On-Ones data to Non-Return-To-Zero format

NRZ format data is the natural data format that the receiver

block utilizes internally so this function is required when the

standard NRZI format data is fed into the device The re-

ceiver block can bypass this conversion function in the case

where an alternate data source outputs NRZ format data

This function can be enabled and disabled through bit 7

(RNRZ) of the Mode Register (MR) When the bit is cleared

it converts the incoming bit stream from NRZI to NRZ This

is the normal configuration required When the bit is set the

incoming NRZ bit stream is passed unchanged

SHIFT REGISTER

The Shift Register converts the serial bit stream into sym-

bol-wide data for the 5B4B Decoder

The Shift Register also provides byte-wide data for the

Framing Logic

FRAMING LOGIC

The Framing Logic performs the Framing function by detect-

ing the beginning of a frame or the Halt-Halt or Halt-Quiet

symbol pair

The J-K symbol pair (11000 10001) indicates the beginning

of a frame during normal operation The Halt-Halt (00100

00100) and Halt-Quiet (00100 00000) symbol pairs are de-

tected for Connection Management (CMT)

TLF11708 – 4

FIGURE 3-2 Receiver Block Diagram

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