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OPA820 Datasheet(PDF) 4 Page - Texas Instruments

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Part # OPA820
Description  12-Bit, Serial Input, Multiplying Digital-to-Analog Converter
PDF  24 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

OPA820 Datasheet(HTML) 4 Page - Texas Instruments

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PIN DESCRIPTION
MSOPPACKAGE
(TOPVIEW)
1
2
3
4
5
10
9
8
7
6
I
1
OUT
I
2
OUT
GND
SCLK
SDIN
R
FB
V
REF
V
DD
SDO
SYNC
DAC7811
SBAS337C – APRIL 2005 – REVISED JULY 2007
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NO.
NAME
1
IOUT1
DAC Current Output
2
IOUT2
DAC Analog Ground. This pin is normally tied to the analog ground of the system.
3
GND
Ground pin.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input.
4
SCLK
Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift
register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default,
5
SDIN
on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to
change the active edge to the rising edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
6
SYNC
edge of the following clocks (power-on default is falling clock edge). In stand-alone mode, the serial interface counts
the clocks and data is latched to the shift register on the 16th active clock edge.
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked out on the
7
SDO
alternate edge to loading data to the shift register. Writing the Readback control word to the shift register makes the
DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock
edge.
8
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.7V to 5.5V.
9
VREF
DAC Reference Voltage Input
10
RFB
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
4
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