AD7908 datasheet(14/24 Pages) AD

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AD7908/AD7918/AD7928

REV. A

Table II. Channel Selection

ADD2

ADD1

ADD0

Analog Input Channel

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

Table III. Power Mode Selection

PM1 PM0 Mode

Normal Operation. In this mode, the AD7908/

AD7918/AD7928 remain in full power mode

regardless of the status of any of the logic inputs.

This mode allows the fastest possible throughput

rate from the AD7908/AD7918/AD7928.

Full Shutdown. In this mode, the AD7908/

AD7918/AD7928 is in full shutdown mode with

all circuitry powering down. The AD7908/AD7918/

AD7928 retains the information in the Control

full shutdown until these bits are changed.

Auto Shutdown. In this mode, the AD7908/

AD7918/AD7928 automatically enters full

shutdown mode at the end of each conversion

when the control register is updated. Wake-up

time from full shutdown is 1 µs and the user

should ensure that 1 µs has elapsed before

attempting to perform a valid conversion on the

part in this mode.

Invalid Selection. This configuration is not allowed.

SEQUENCER OPERATION

The configuration of the SEQ and SHADOW bits in the

Control Register allows the user to select a particular mode of

operation of the sequencer function. Table IV outlines the four

modes of operation of the Sequencer.

Table IV. Sequence Selection

SEQ SHADOW

Sequence Type

This configuration means that the sequence

function is not used. The analog input

channel selected for each individual

conversion is determined by the contents of

the channel address bits ADD0 through

ADD2 in each prior write operation. This

mode of operation reflects the traditional

operation of a multichannel ADC, without

the Sequencer function being used, where

each write to the AD7908/AD7918/

AD7928 selects the next channel for

conversion. (See Figure 2.)

This configuration selects the SHADOW

write operation will load the contents of the

SHADOW Register. This will program the

sequence of channels to be converted on

continuously with each successive valid

falling edge. (See SHADOW Register

section, Table V, and Figure 3.) The

channels selected need not be consecutive.

If the SEQ and SHADOW bits are set in

this way, then the sequence function will

not be interrupted upon completion of the

WRITE operation. This allows other bits in

the Control Register to be altered between

conversions while in a sequence, without

terminating the cycle.

This configuration is used in conjunction

with the channel address bits ADD2 to

ADD0 to program continuous conversions

on a consecutive sequence of channels from

Channel 0 to a selected final channel as

determined by the channel address bits in

the Control Register. (See Figure 4.)

–14–

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