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AD7475ARM Datasheet(PDF) 4 Page - Analog Devices |
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AD7475ARM Datasheet(HTML) 4 Page - Analog Devices |
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4 / 16 page  REV. A –4– AD7475/AD7495–SPECIFICATIONS1 AD7495–SPECIFICATIONS (continued) Parameter A Version 1 B Version 1 Unit Test Conditions/Comments CONVERSION RATE Conversion Time 800 800 ns max 16 SCLK Cycles with SCLK at 20 MHz Track/Hold Acquisition Time 300 300 ns max Sine Wave Input 325 325 ns max Full-Scale Step Input Throughput Rate 1 1 MSPS max See Serial Interface Section POWER REQUIREMENTS VDD 2.7/5.25 2.7/5.25 V min/max VDRIVE 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or VDRIVE Normal Mode (Static) 1 1 mA typ VDD = 2.7 V to 5.25 V. SCLK On or Off Normal Mode (Operational) 2.6 2.6 mA max VDD = 4.75 V to 5.25 V. fSAMPLE = 1 MSPS 2 2 mA max VDD = 2.7 V to 3.6 V. fSAMPLE = 1 MSPS Partial Power-Down Mode 650 650 µA typ fSAMPLE = 100 kSPS Partial Power-Down Mode 230 230 µA max (Static) Full Power-Down Mode 1 1 µA max (Static) SCLK On or Off Power Dissipation 3 Normal Mode (Operational) 13 13 mW max VDD = 5 V. fSAMPLE = 1 MSPS 6 6 mW max VDD = 3 V. fSAMPLE = 1 MSPS Partial Power-Down (Static) 1.15 1.15 mW max VDD = 5 V 690 690 µW max VDD = 3 V Full Power-Down 5 5 µW max VDD = 5 V 33 µW max VDD = 3 V NOTES 1Temperature ranges as follows: A, B Versions: –40 C to +85 C. 2Sample tested @ 25 C to ensure compliance. 3See Power Versus Throughput Rate section. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475); TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX Parameter AD7475/AD7495 Unit Description fSCLK 2 10 kHz min 20 MHz max tCONVERT 16 × t SCLK tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 100 ns min Minimum Quiet Time Required between Conversions t2 10 ns min CS to SCLK Setup Time t3 3 22 ns max Delay from CS Until SDATA 3-State Disabled t4 3 40 ns max Data Access Time after SCLK Falling Edge t5 0.4 tSCLK ns min SCLK Low Pulsewidth t6 0.4 tSCLK ns min SCLK High Pulsewidth t7 10 ns min SCLK to Data Valid Hold Time t8 4 10 ns min SCLK Falling Edge to SDATA High Impedance 45 ns max SCLK Falling Edge to SDATA High Impedance t9 4 20 ns max CS Rising Edge to SDATA High Impedance tPOWER-UP 20 µs max Power-Up Time from Full Power-Down AD7475 650 µs max Power-Up Time from Full Power-Down AD7495 NOTES 1Sample tested at 25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DRIVE) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t 8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are the true bus relinquish time of the part and are independent of the bus loading. Specifications subject to change without notice. |
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