REV. A

AD7475/AD7495

–12–

cycle of 16 SCLKs must always elapse to power up the device

µs will be sufficient to power the device

up and acquire the input signal. If, for example, a 5 MHz SCLK

frequency was applied to the ADC, the cycle time would be 3.2 s.

In one dummy cycle, 3.2

µs, the part would be powered up and

µs with a 5 MHz SCLK,

only 5 SCLK cycles would have elapsed. At this stage, the ADC

would be fully powered up and the signal acquired. So, in this

case the

CS can be brought high after the tenth SCLK falling edge

Full Power-Down Mode

This mode is intended for use in applications where slower

throughput rates are required than that in the partial power-down

mode, as power up from a full power-down would not be com-

plete in just one dummy conversion. This mode is more suited to

applications where a series of conversions performed at a relatively

high throughput rate would be followed by a long period of

inactivity and hence power-down. When the AD7475/AD7495

is in full power-down, all analog circuitry is powered down.

Full power-down is entered in a way similar to partial power-down,

except the timing sequence shown in Figure 14 must be executed

twice. The conversion process must be interrupted in a similar

fashion by bringing

CS high anywhere after the second falling

edge of SCLK and before the tenth falling edge of SCLK. The

device will enter partial power-down at this point. To reach full

power-down, the next conversion cycle must be interrupted

in the same way as shown in Figure 16. Once

CS has been

brought high in this window of SCLKs, then the part will

power down completely.

NOTE: It is not necessary to complete the 16 SCLKs once

CS

has been brought high to enter a power-down mode.

To exit full power-down, and power the AD7475/AD7495 up

again, a dummy conversion is performed as when powering

up from partial power-down. On the falling edge of

CS the

device will begin to power up, and will continue to power up as

long as

CS is held low until after the falling edge of the tenth

SCLK. The power-up time is longer than one dummy conversion

a conversion can be initiated as shown in Figure 17. (See

Timing Specifications.)

When power supplies are first applied to the AD7475/AD7495,

the ADC may power up in either of the power-down modes or

normal mode. Because of this, it is best to allow a dummy cycle

to elapse to ensure the part is fully powered up before attempt-

ing a valid conversion. Likewise, if it is intended to keep the part

in the partial power-down mode immediately after the supplies

are applied, then two dummy cycles must be initiated. The first

dummy cycle must hold

CS low until after the tenth SCLK

falling edge, Figure 13; in the second cycle

CS must be brought

high before the tenth SCLK edge but after the second SCLK

falling edge, Figure 14. Alternatively, if it is intended to place

the part in full power-down mode when the supplies have been

applied, then three dummy cycles must be initiated. The first

dummy cycle must hold

CS low until after the tenth SCLK

edge, Figure 13; the second and third dummy cycle place the

part in full power-down, Figure 16. See Modes of Operation

section. Once supplies are applied to the AD7475/AD7495,

enough time must be allowed, for the AD7475, for the external

reference to power up and charge the reference capacitor to its

final value. For the AD7495, enough time should be allowed for

the internal reference buffer to charge the reference capacitor.

Then, to place the AD7475/AD7495 in normal mode, a dummy

cycle, 1

µs, should be initiated. If the first valid conversion is then

performed directly after the dummy conversion, care must be

taken to ensure that adequate acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down

mode, the part will return to track upon the first SCLK edge

applied after the falling edge of

CS. However, when the ADC

powers up initially after supplies are applied, the track-and-hold

will already be in track. This means (assuming one has the facil-

ity to monitor the ADC supply current) if the ADC powers up

SCLK

CS

SDATA

INVALID DATA

INVALID DATA

1

10

16

1

THE PART BEGINS

TO POWER UP

16

2

10

2

THE PART ENTERS

FULL POWER-DOWN

THE PART ENTERS

PARTIAL POWER-DOWN

THREE-STATE

THREE-STATE

Figure 16. Entering Full Power-Down Mode

SCLK

CS

SDATA

INVALID DATA

VALID DATA

1

10

16

1

THE PART BEGINS

TO POWER UP

THE PART IS FULLY

POWERED UP

16

Figure 17. Exiting Full Power-Down Mode