REV. A

AD7475/AD7495

–8–

AD7475/AD7495 TYPICAL PERFORMANCE CURVES

TPC 1 shows a typical FFT plot for the AD7475 at 1 MHz

sample rate and 100 kHz input frequency.

FREQUENCY – kHz

–115

0

50

100

150

200

250

300

–95

–75

–55

–35

350

400

500

450

–15

8192 POINT FFT

SINAD = 70.46dB

THD = –87.7dB

SFDR = –89.5dB

TPC 1. AD7475 Dynamic Performance

TPC 2 shows a typical FFT plot for the AD7495 at 1 MHz sample

rate and 100 kHz input frequency.

FREQUENCY – kHz

–115

0

50

100

150

200

250

300

–95

–75

–55

–35

350

400

500

450

–15

8192 POINT FFT

SINAD = 69.95dB

THD = –89.2dB

SFDR = –91.2dB

TPC 2. AD7495 Dynamic Performance

TPC 3 shows the signal-to-(noise + distortion) ratio performance

versus input frequency for various supply voltages while sampling

at 1 MSPS with an SCLK of 20 MHz.

INPUT FREQUENCY – kHz

68.5

10

100

69.0

69.5

70.0

70.5

1000

71.0

TPC 3. AD7495 SINAD vs. Input Frequency at 1 MSPS

CIRCUIT INFORMATION

The AD7475/AD7495 are fast, micropower, 12-bit, single-supply,

A/D converters. The parts can be operated from a 2.7 V to 5.25 V

supply. When operated from either a 5 V supply or a 3 V sup-

ply, the AD7475/AD7495 are capable of throughput rates of

1 MSPS when provided with a 20 MHz clock.

The AD7475/AD7495 provide the user with an on-chip track/

hold, A/D converter, and a serial interface housed in either an

8-lead SOIC or

µSOIC package, which offers the user considerable

space-saving advantages over alternative solutions. The AD7495

also has an on-chip 2.5 V reference. The serial clock input accesses

data from the part but also provides the clock source for the

successive-approximation A/D converter. The analog input range

is 0 V to REF IN for the AD7475 and 0 V to REF OUT for

the AD7495.

The AD7475/AD7495 also feature power-down options to allow

power saving between conversions. The power-down feature is

implemented across the standard serial interface as described in

the Modes of Operation section.

CONVERTER OPERATION

The AD7475/AD7495 are 12-bit successive approximation

analog-to-digital converters based around a capacitive DAC.

The AD7475/AD7495 can convert analog input signals in the

range 0 V to 2.5 V. Figures 4 and 5 show simplified schematics

of the ADC. The ADC comprises of Control Logic, SAR and a

Capacitive DAC, which are used to add and subtract fixed

amounts of charge from the sampling capacitor to bring the

comparator back into a balanced condition. Figure 4 shows the

ADC during its acquisition phase. SW2 is closed and SW1 is in

Position A. The comparator is held in a balanced condition and

COMPARATOR

CONTROL LOGIC

CAPACITIVE

DAC

AGND

4k

SW2

SW1

A

B

Figure 4. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 5), SW2 will

open and SW1 will move to position B causing the compara-

tor to become unbalanced. The Control Logic and the Capacitive

DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The Control Logic generates the ADC

output code. Figure 6 shows the ADC transfer function.

COMPARATOR

CONTROL LOGIC

CAPACITIVE

DAC

AGND

4k

SW2

SW1

A

B

Figure 5. ADC Conversion Phase