REV. B

–14–

AD8033/AD8034

bipolar pair Q25 and Q27. With this configuration, the inputs

can be driven beyond the positive supply rail without any phase

inversion (see Figure 3).

As a result of entering the bipolar mode of operation, an offset and

input bias current shift will occur. See TPCs 27 and 30. After

re-entering the JFET common-mode range, the amplifier will

recover in approximately 100 ns (refer to TPC 24 for input

overload behavior). Above and below the supply rails, ESD pro-

tection diodes activate, resulting in an exponentially increasing

input bias current. If the inputs are to be driven well beyond the

rails, series input resistance should be included to limit the input

bias current to less than 10 mA.

Input Impedance

The input capacitance of the AD8033/AD8034 will form a pole

with the feedback network, resulting in peaking and ringing in the

overall response. The equivalent impedance of the feedback

network should be kept small enough to ensure that the parasitic

pole falls well beyond the –3 dB bandwidth of the gain configura-

tion being used. If larger impedance values are desired, the

amplifier can be compensated by placing a small capacitor in

parallel with the feedback resistor. TPC 8 shows the improvement

in frequency response by including a small feedback capacitor

with high feedback resistance values.

Thermal Considerations

Because the AD8034 operates at up to

±12 V supplies in the small

SOT-23-8 package (160

°C/W), power dissipation can easily exceed

package limitations, resulting in permanent shifts in device

characteristics and even failure. Likewise, high supply voltages can

cause an increase in junction temperature even with light loads,

resulting in an input bias current and offset drift penalty. The input

bias current will double for every 10

°C shown in TPC 26. Refer

to the Maximum Power Dissipation section for an estimation of

die temperature based on load and supply voltage.

THEORY OF OPERATION

The incorporation of JFET devices into Analog Devices’ high

voltage XFCB process has given the performance ability to

design the AD8033/AD8034. The AD8033/AD8034 are voltage

feedback rail-to-rail output amplifiers with FET inputs and a

bipolar-enhanced common-mode input range. The use of JFET

devices in high speed amplifiers extends the application space

into both low input bias current as well as low distortion high

bandwidth areas.

Using N-channel JFETs and a folded cascade input topology, the

common-mode input level operates from 0.2 V below the negative

rail to within 3.0 V of the positive rail. Cascading of the input stage

ensures low input bias current over the entire common-mode range

as well as CMRR and PSRR specifications that are above 90 dB.

Additionally, long-term settling issues that normally occur with

high supply voltages are minimized as a result of the cascading.

Output Stage Drive and Capacitive Load Drive

The common emitter output stage adds rail-to-rail output perfor-

mance and is compensated to drive 35 pF (30% overshoot G = +1).

Additional capacitance can be driven if a small snub resistor is

put in series with the capacitive load, effectively decoupling the

load from the output stage, as shown in TPC 7. The output

stage can source and sink 20 mA of current within 500 mV of the

supply rails and 1 mA within 100 mV of the supply rails.

Input Overdrive

An additional feature of the AD8033/AD8034 is a bipolar

input pair that adds rail-to-rail common-mode input perfor-

mance specifically for applications that cannot tolerate phase

inversion problems.

Under normal common-mode operation, the bipolar input pair

input common mode comes within 3.0 V of the positive supply

rail, I1 turns off and I4 turns on, supplying tail current to the

VTH

+VS

R2

Q6

–IN

J1

D4

Q25

Q7

I2

Q27

R3

R14

Q9

–VS

I1

I4

J2

+IN

R7

Q29

Q4

Q13

VCC

Q11

I3

Q28

R8

Q1

Q14

V2

V4

+

+

–

–

D5

Figure 3. Simplified AD8033/AD8034 Input Stage