AD8033 datasheet(16/20 Pages) AD

16 / 20 page

REV. B

–16–

AD8033/AD8034

Using the AD8033/AD8034, a unity gain peak detector can be

constructed that will capture a 300 ns pulse while still taking

advantage of the AD8033/AD8034’s low input bias current and

wide common-mode input range, as shown in Figure 5.

Using two amplifiers, the difference between the peak and the

current input level is forced across R2 instead of either amplifier’s

input pins. In the event of a rising pulse, the first amplifier

compensates for the drop across D2 and D3, forcing the voltage at

Node 3 equal to Node 1. D1 is off and the voltage drop across R2

is zero. Capacitor C3 speeds up the loop by providing the charge

required by the first amplifier’s input capacitance, helping to

maintain a minimal voltage drop across R2 in the sampling mode.

A negative going edge results in D2 and D3 turning off and D1

turning on, closing the loop around the first amplifier and forcing

VOUT – VIN across R2. R4 makes the voltage across D2 zero,

minimizing leakage current and kickback from D3 from affecting

the voltage across C2.

The rate of the incoming edge must be limited so that the output

of the first amplifier does not overshoot the peak value of VIN

before the second amplifier’s output can provide negative feedback

at the first amplifier’s summing junction. This is accomplished

with the combination of R1 and C1, which allows the voltage at

Node 1 to settle to 0.1% of VIN in 270 ns. The selection of C2

and R3 is made by considering droop rate, settling time, and

kickback. R3 prevents overshoot from occurring at Node 3. The

time constants of R1, C1 and R3, C2 are roughly equal to achieve

the best performance. Slower time constants can be selected by

increasing C2 to minimize droop rate and kickback at the cost

of increased settling time. R1 and C1 should also be increased

to match, reducing the incoming pulse’s effect on kickback.

INPUT

OUTPUT

1.00V/DIV

100nS/DIV

Figure 6. Peak Detector Response 4 V 300 ns Pulse

Figure 6 shows the peak detector in Figure 5 capturing a 300 ns

4 V pulse with 10 mV of kickback and a droop rate of 5 V/s. For

larger peak-peak pulses, the time constants of R1, C1 and R3, C3

should be increased to reduce overshoot. The best droop rate will

occur by isolating parasitic resistances from Node 3. This can be

accomplished using a guard band connected to the output of the

second amplifier that surrounds its summing junction (Node 3).

Increasing both time constants by a factor of 3 permits a larger

peak pulse to be captured and increases the output accuracy.

AD8034

1/2

10pF

AD8034

1/2

–VS

+VS

39pF/

120pF

LS4148

VIN

49.9

4.7pF

LS4148

–VS

+VS

LS4148

200

180pF/560pF

VOUT

Figure 5. High Speed Unity Gain Peak Detector Using AD8034

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