ADV7301A datasheet(34/68 Pages) AD

34 / 68 page

REV. A

–34–

ADV7300A/ADV7301A

Table XIV. Truth Table

P_HSYNC

P_VSYNC1

P_BLANK

Reference

→ 0

0 or 1

50% point of falling edge of tri-level horizontal sync signal

→ 1

0 or 1

25% point of rising edge of tri-level horizontal sync signal

→ 1

0 or 1

50% point of falling edge of tri-level horizontal sync signal

10 or 1

→ 1

50% start of active video

10 or 1

→ 0

50% end of active video

NOTES

For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.

1When Async Timing Mode is enabled, P_BLANK, Pin 25 becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.

2See Figure 28.

LCC1

GLL

P19–P10

ADV7185

VIDEO

DECODER

COMPOSITE

VIDEO1

CLKIN_A

RTC_SCR_TR

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

S9–S0

RTC

LOW

H/L TRANSITION

COUNT START

128

TIME SLOT 01

14 BITS

RESERVED

FSC PLL INCREMENT2

VALID

SAMPLE

INVALID

SAMPLE

8/LINE

LOCKED

CLOCK

6768

4 BITS

RESERVED

SEQUENCE

BIT3

RESET

BIT4

RESERVED

5 BITS

RESERVED

ADV7300A/

ADV7301A

NOTES

1i.e., VCR OR CABLE

SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7300A/ADV7301A FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS

OF THE ADV7300A/ADV7301A.

3PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE

4RESET ADV7300A/ADV7301A DDS

NOT USED

Figure 29. RTC Timing and Connections

SD VCR FF/RW Sync

[Subaddress 42h, Bit 5]

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW Sync Control Bit can be used for

nonstandard input video, i.e., in Fast Forward or Rewind Modes.

In Fast Forward Mode, the sync information for the start of a

new field in the incoming video usually occurs before the total

number of lines/fields are reached; in Rewind Mode, this sync

signal occurs usually after the total number of lines/fields are

reached. Conventionally, this means that the output video will

have an erroneous start of new field signals, one generated by the

incoming video and one when the internal lines/field counters

reach the end of a field. When VCR FF/RW sync control is en-

abled [Subaddress 42h, Bit 5], the lines/field counters are

updated according to the incoming VSYNC signal, and the ana-

log output matches the incoming VSYNC signal.

This control is available in all slave timing modes except Slave

Mode 0.

RESET SEQUENCE

A reset is activated with a high-to-low transition on the

RESET

pin (Pin 33) according to the timing specifications. The

ADV7300A/ADV7301A will revert to the default output con-

figuration. Figure 30 illustrates the

RESET sequence timing.

RESET

DIGITAL TIMING

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

VALID VIDEO

TIMING ACTIVE

DACs

PIXEL DATA

VALID

Figure 30.

RESET Timing Sequence

ADV7301A Datasheet(PDF) 34 Page - Analog Devices

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