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DP8422A Datasheet(PDF) 52 Page - National Semiconductor (TI) |
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DP8422A Datasheet(HTML) 52 Page - National Semiconductor (TI) |
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52 / 58 page  130 AC Timing Parameters (Continued) Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs per bank including trace capacitance (Note 2) Two different loads are specified CL e 50 pF loads on all outputs except CL e 150 pF loads on Q0–8 9 10 and WE or CH e 50 pF loads on all outputs except CH e 125 pF loads on RAS0–3 and CAS0–3 and CH e 380 pF loads on Q0–8 9 10 and WE Mode 1 Access 8420A21A22A-20 8420A21A22A-25 Number Symbol Parameter Description CL CH CL CH Min Max Min Max Min Max Min Max 400a tSADSCK1 ADS Asserted Setup to CLK High 15 15 13 13 400b tSADSCKW ADS Asserted Setup to CLK (to Guarantee Correct WAIT 31 31 25 25 or DTACK Output Doesn’t Apply for DTACK0) 401 tSCSADS CS Setup to ADS Asserted 6 6 5 5 402 tPADSRL ADS Asserted to RAS Asserted 30 35 25 29 403a tPADSCL0 ADS Asserted to CAS Asserted 86 94 75 82 (tRAH e 15 ns tASC e 0 ns) 403b tPADSCL1 ADS Asserted to CAS Asserted 96 104 85 92 (tRAH e 15 ns tASC e 10 ns) 403c tPADSCL2 ADS Asserted to CAS Asserted 96 104 85 92 (tRAH e 25 ns tASC e 0 ns) 403d tPADSCL3 ADS Asserted to CAS Asserted 106 114 95 102 (tRAH e 25 ns tASC e 10 ns) 404 tSADDADS Row Address Valid Setup to ADS 913914 Asserted to Guarantee tASR e 0ns 405 tHCKADS ADS Negated Held from CLK High 0 0 0 0 406 tSWADS WAITIN Asserted Setup to ADS Asserted to Guarantee DTACK0 0 000 Is Delayed 407 tSBADAS Bank Address Setup to ADS Asserted 11 11 11 11 408 tHASRCB Row Column Bank Address Held from 10 10 10 10 ADS Asserted (Using On-Chip Latches) 409 tSRCBAS Row Column Bank Address Setup to 3322 ADS Asserted (Using On-Chip Latches) 410 tWADSH ADS Negated Pulse Width 12 16 12 17 411 tPADSD ADS Asserted to DTACK Asserted 43 43 35 35 (Programmed as DTACK0) 412 tSWINADS WIN Asserted Setup to ADS Asserted (to Guarantee CAS Delayed during b 10 b 10 b 10 b 10 Writes Accesses) 413 tPADSWL0 ADS Asserted to WAIT Asserted 35 35 29 29 (Programmed as WAIT0 Delayed Access) 414 tPADSWL1 ADS Asserted to WAIT Asserted 35 35 29 29 (Programmed WAIT 12 or 1) 415 tPCLKDL1 CLK High to DTACK Asserted (Programmed as DTACK0 40 40 32 32 Delayed Access) 416 AREQ Negated to ADS Asserted to Guarantee tASR e 0 ns 38423136 (Non Interleaved Mode Only) 417 tPADSCV0 ADS Asserted to Column Address Valid 83 92 69 78 (tRAH e 15 ns tASC e 0 ns) 52 |
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