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DP8422A Datasheet(PDF) 56 Page - National Semiconductor (TI) |
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DP8422A Datasheet(HTML) 56 Page - National Semiconductor (TI) |
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56 / 58 page  130 AC Timing Parameters (Continued) Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs per bank including trace capacitance (Note 2) Two different loads are specified CL e 50 pF loads on all outputs except CL e 150 pF loads on Q0–8 9 10 and WE or CH e 50 pF loads on all outputs except CH e 125 pF loads on RAS0–3 and CAS0–3 and CH e 380 pF loads on Q0–8 9 10 and WE Programming 8420A21A22A-20 8420A21A22A-25 Number Symbol Parameter Description CL CH CL CH Min Max Min Max Min Max Min Max 500 tHMLADD Mode Address Held from ML Negated 8 8 7 7 501 tSADDML Mode Address Setup to ML Negated 6 6 6 6 502 tWML ML Pulse Width 15 15 15 15 503 tSADAQML Mode Address Setup to AREQ Asserted 0 0 0 0 504 tHADAQML Mode Address Held from AREQ Asserted 51 51 38 38 505 tSCSARQ CS Asserted Setup to 6666 AREQ Asserted 506 tSMLARQ ML Asserted Setup to AREQ Asserted 10 10 10 10 TLF8588 – F7 FIGURE 44 500 Programming 56 |
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