S

W

Slave Address

(7 bits)

Control Register Add.

(8 bits)

A

A

A

Register Data

(8 bits)

P

From Master to Slave

From Slave to Master

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

W - WRITE

SDA

SCL

S

P

STO

SCL

SDA

data

change

allowed

data valid

data

change

allowed

data valid

data

change

allowed

LM3549

SNVS640A – AUGUST 2010 – REVISED MAY 2013

www.ti.com

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

The I2C bus is considered to be busy after START condition and free after STOP condition. During data

conditions are equivalent, function-wise.

Figure 22. Start and Stop Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the ninth clock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

eighth bit which is a data direction bit (R/W). The LM3549 address is 36 hex. For the eighth bit, a “0” indicates a

WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

14

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