DP8464B datasheet(12/26 Pages) NSC

12 / 26 page

Application Information (Continued)

This time can be decreased by placing an external resistor

across the CAGC For instance if a 100k resistor is placed in

parallel with CAGC then the discharge current is 40 mA The

time required to increase the amplifier gain is now 40 times

faster or 275 ms If this external resistor is made even small-

er say 10k then the discharge time will go to 275 ms Now

however there is another problem introduced The re-

sponse time of the AGC is so fast that it distorts the signal

at the output of the Gain Controlled Amplifier Distortion of

the signal at the Amplifier Output can affect the time posi-

tion of the peaks of this signal Be sure to check this distor-

tion over the range of input levels you expect to encounter

when choosing the external R and C values for the AGC

If the value of the bleed resistor across the CAGC is de-

creased (in order to equalize the AGC attack and decay

times) the value of CAGC must be increased in order to

maintain an AGC response that does not distort the signal

There is a second order effect on the amplitude that results

from this attack and decay time equalization Referring to

Figure 2 notice that the AGC is driven from a full wave

rectified version of the Gate Channel Input signal When the

AGC is operated normally (ie fast attack and slow decay)

the voltage that appears across CAGC is the peak detected

value of this full wave rectified waveform However if you

equalize the AGC attack and decay times the voltage

across CAGC is the RMS voltage (0707 times the peak) of

the full wave rectified waveform Thus the voltage across

CAGC is less and the amplitude out of the Gain Controlled

Amplifier will consequently be 14 times larger

It is possible to externally drive the CAGC pin to control the

gain of the amplifier It must be noted that the gain of the

amplifier is not always exactly 200 when the voltage on

CAGC is 34V The transfer curve between the gain of the

amplifier and the voltage on CAGC is only approximate This

transfer curve will vary between parts and with temperature

Care should be taken to prevent the voltage on the CAGC

pin from going below ground or above 55V

Figure 7 shows

a typical curve of the Gain Controlled Amplifier Gain vs the

voltage across CAGC (Vpin 16)

TLF5283 – 12

FIGURE 7 Gain Controlled Amplifier Gain vs Vpin 16

It is possible to change the time constant of the AGC circuit

by switching in different external components at the desired

times For instance as shown in

Figure 8 an external open

collector TTL gate and resistor can be added in parallel with

CAGC to decrease the AGC response time Similarly an ex-

ternal capacitor could be switched in to increase the re-

sponse time Since in the absence of an external resistor

the discharge time of CAGC is much longer than the attack

time there may be some applications where it is desirable to

switch in a parallel resistor to quickly discharge CAGC then

switch it out to force a quick attack Because of the quick

attack time the AGC obtains the proper level quicker than it

would had CAGC simply been allowed to discharge to the

new level

There are some applications where it is desirable to hold the

AGC level for a period of time This can be done by raising

the READ WRITE pin This will shut off the input circuitry

and it will take time (about 25 ms) for the circuit to recover

when going back into the read mode

Figure 9 shows a

method to hold the AGC level while remaining in the read

mode (which could be used in embedded servo applica-

tions) If the voltage on VREF is raised to 3V then the ampli-

fier output voltage cannot get large enough to turn on the

circuitry to charge up CAGC For this to work properly there

can not be a large discharge current path (resistor in parallel

with CAGC) across CAGC The AGC block can be bypassed

altogether by connecting VREF to 3V In this way the user

can use his own AGC circuit to drive the CAGC pin directly

TLF5283 – 13

FIGURE 8 Circuit to Decrease AGC Response Time

TLF5283 – 14

FIGURE 9 Circuit for AGC Hold

READ WRITE

In the normal read mode the signal from the readwrite

head amplifier is in the range of 20 mVpp to 660 mVpp

However when data is being written to the disk the signal

coming into the analog input of the pulse detector will be on

the order of 600 mV Such a large signal will disturb the

AGC level and would probably saturate the amplifier In ad-

dition if a different readwrite amplifier is selected there will

be a transient introduced because the offset of the pream-

plifiers are not matched A READ WRITE input pin has

been provided to minimize these effects to the pulse detec-

tor This is a standard TTL input

When the READ WRITE pin is low the pulse detector is in

the read mode When the READ WRITE pin is taken high

three things happen First the 1k resistors across the AMP

IN pins are shunted by 300X resistors as described previ-

ously in the Gain Controlled Amplifier section Next the am-

plifier is squelched so there is no signal on the Amp Output

DP8464B Datasheet(PDF) 12 Page - National Semiconductor (TI)

DP8464B Datasheet(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL