DP8464B datasheet(23/26 Pages) NSC

23 / 26 page

Application Information (Continued)

PARTS LIST FOR DP8464B BOARD

Component

Note

Function

Value for

Name

Value

5 Mbitssec

10 Mbitssec

Adjustment for VREF (AGC amplitude)

1k pot

Adjustment for Set Hyst (threshold)

1k pot

Adjustment for differentiator network Q

5k pot

Low pass filter resistor

560X

Low pass filter resistor

240X

Low pass filter resistor

240X

Amp Out emitter bias resistor

43k

Amp Out emitter bias resistor

43k

R10

Pull down resistor for ReadWrite Pin

51k

R11

Resistor in parallel with CAGC

100k

R12

Encoded Data Out damping resistor

51X

R13

ReadWrite damping resistor

51X

R14

Divider network for Set Hyst and VREF

24k

R17

Series resistor for Time Channel Input

Not required on DP8464B

R18

Series resistor for Time Channel Input

Not required on DP8464B

VREF cap

01 mF

Set Hyst cap

01 mF

Differentiator cap

100 pF

50 pF

Time and Gate Channel In coupling cap

001 mF

Time and Gate Channel In coupling cap

001 mF

Low pass filter cap

200 pF

100 pF

Low pass filter cap

30 pF

15 pF

CAGC cap

001 mF

C10

VCC cap

10 mF

C11

VCC cap

01 mF

C13

Amp In coupling cap

2200 pF

C14

Amp In coupling cap

2200 pF

C16

Set Pulse Width cap

100 pF

50 pF

Differentiator inductor

36 mH

16 mH

Low pass filter inductor

10 mH

47 mH

Low pass filter inductor

10 mH

47 mH

BREADBOARD OPERATION NOTES

1 The low pass filter is a 3 pole Bessel with the corner

frequency at 375 MHz for the 5Mbitssec board (75

MHz for the 10 Mbitssec board)

2 The differentiator is a simple RLC filter with the break

frequency at 85 MHz for the 5 Mbitssec board (17 MHz

for the 10 Mbitssec board) The resistor can be adjusted

to correct for phase distortion in the channel

3 The VREF should be set at 05V Since the low pass filter

hasa6dB loss the signal on AMP OUT is 4 Vpp differen-

tial while the amplitude into the gate channel is 2 Vpp

differential The Set Hyst should be nominally set at

03V

4 The AGC attack time (the response to an increased input

amplitude) is about 2 ms To increase this time increase

the value of C8 (the AGC capacitor) The AGC decay time

(the response to a decrease in amplitude) is about 10 ms

To increase this time increase the value of R11 Care

must be taken to not allow the response of the AGC loop

to become too fast otherwise loop instability may occur

5 The input pole is set at 72 kHz (1k input impedance and a

2200 pF input coupling capacitor)

6 Pulse pairing (described in the differentiator section of

this data sheet) can be caused by unequal delays through

the Bi-directional one shots To minimize this effect pin 2

should be connected to pin 22 and pin 23 should be

connected to pin 21 If connected this way the delays

tend to cancel

REFERENCES

1 I H Graham ‘‘Data Detection Methods vs Head Resolu-

tion in Digital Recording’’ IEEE Transactions on Magnet-

ics Vol MAG-14 No 4 (July 1978)

2 I H Graham ‘‘Digital Magnetic Recording Circuits’’ to be

published

3 Anatol I Zverev Handbook of Filter Synthesis John Wi-

ley

Sons publisher 1967

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