DP8464B datasheet(14/26 Pages) NSC

14 / 26 page

Application Information (Continued)

TLF5283 – 17

FIGURE 12 Simplified Differentiator First Stage

across the external differentiator network (Cd in series with

Rd) is the differential input voltage V1 b V2 When Rd is

zero the current through Cd is I e C c (dVdt) or Cd c

(dVIN dt) The Q2 collector current is the sum of the 18 mA

current source plus the current through Cd or

18 mA a Cd c (dVIN dt)

Similarly the Q3 collector current is

18 mA b Cd c (dVIN dt)

Therefore the differentiator output voltage V5 b V6 is

15k c 2 c Cd c (dVIN dt)

The input is at a peak when V5 b V6 e 0V

The differentiator network (Cd and Rd) should be selected

so the maximum current into the differentiator network is not

greater than the minimum current of I1 and I2 over tempera-

ture In the electrical specifications the minimum current is

specified for 14 mA (ICd Current into Pin 1 and 24 that

discharges Cd) For example the highest analog frequency

in a 10 Megabitsec MFM signal is 5 MHz Since the AGC

loop has forced the input to the differentiator to 2 VPP

(which includes the 6 dB loss of the filter) then the voltage

across the capacitor (assuming Rd is 0) is

VIN e 1 c sin(2 c q c 5E6 c t)

and

dVIN dt e 1 c 2 c q c 5E6 c cos(2 c q c 5E6 c t)

and the maximum slope is

(dVIN dt)max e 1 c 2 c q c 5E6 e 314E5 Vsec

For this example Cd can now be calculated Since I e C c

(dVdt) then for I e 14 mA dVdt e 314E5 then the

maximum Cd must equal 45 pF From this example a follow-

ing simple design equation for the value of Cd can be de-

rived

Cd e 445(VIN c fmax)

where

Cd is the maximum external differentiator capacitor in pF

VIN is the peak to peak differential Time Channel input

voltage

fmax is the maximum analog frequency in MHz

Note that this is the maximum value for the capacitor when

the series resistor Rd is zero The value of the capacitor can

be increased if a series resistor is used but the maximum

current through the differentiator network must not exceed

14 mA If too large a value for Cd is used the delay through

the differentiator will become dependent on frequency This

will not show up in a single frequency test such as a test for

pulse pairing

For the MFM code the maximum analog frequency is

the

data rate For the

(27) code the maximum analog fre-

quency is

the data rate The above sinusoidal analysis is

valid as long as the highest frequency on the outer track is

nearly sinusoidal If however there is significant shoulder-

ing of this signal then the value of Cd should be reduced

accordingly

The following table summarizes the value of Cd to use for a

2Vpp differential signal to the time channel input

Data Rate

Code

Maximum Frequency

5 mbitssec

MFM

25 MHz

90 pF

5 mbitssec

16 MHz

140 pF

10 mbitssec

MFM

50 MHz

45 pF

10 mbitssec

33 MHz

67 pF

As noted above the value of the capacitor can be increased

if a series resistor is used but the maximum current through

the differentiator network must not exceed 14 mA For ex-

ample the components used in the Pulse Pairing Setup

(see AC Electrical Specifications) are for a typical 10 Mbits

sec MFM drive The combination of the Cd of 50 pF and the

Rd of 430X gives a combined impedance of 768X at the

highest frequency of 5 MHz This gives a maximum current

of 13 mAwell below the 14 mA limit

A resistor is placed in series with Cd in order to bandlimit the

differentiator response This resistor also has an effect on

the phase linearity of the differentiator An ideal differentia-

tor produces an output that is 90 degree phase shifted from

the input regardless of the input frequency The presence of

the series resistor produces an output phase shift that is

less than 90 degrees and changes with the input frequency

This resistor can be used to correct for frequency related

phase problems encountered elsewhere in the read path

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