DP8464B datasheet(15/26 Pages) NSC

15 / 26 page

Application Information (Continued)

To properly decode the information on the disk the read

channel must determine if there is a peak (or a ‘‘1’’) during a

period of time called a detection window The detection win-

dow for MFM and the (27) code is

1(2 c data bit rate)

This detection window must accommodate errors in many

parts of the system including filters data separator and

peak shift variations in the data pattern The pulse pairing of

the DP8464B should be included in the error budget calcu-

lation

Unequal delays through the bi-directional one shots will

contribute to pulse pairing To minimize this effect pin 2

should be connected to 22 and pin 23 should be connected

to 21 If connected this way the delays tend to cancel For

the PCC Package Pin 26 to Pin 2 and Pin 25 to Pin 27

DIFFERENTIAL COMPARATOR WITH HYSTERESIS

The actual peak detection is done in the time channel with

the differentiator Unfortunately the differentiator not only

responds to signal peaks but also responds to noise at the

baseline In order to prevent this noise from generating false

data the signal at the output of the Gain Controlled Amplifi-

er is also passed through a gating channel which prevents

any output change before the input signal has crossed an

established level This gating channel comprises a differen-

tial comparator with hysteresis and a D flip-flop The hyster-

esis for this comparator is set externally via the Set Hystere-

sis pin The amount of hysteresis is twice the voltage on the

Set Hysteresis pin For instance if the voltage on the Set

Hysteresis pin is 03V the differential input signal must be

larger than 06V(g03V) before the output of the compara-

tor will change states The 06V hysteresis represents 30%

of a typical 2V differential input signal level to the

gating channel The hysteresis level is usually set between

15% to 40% of the differential input signal

The operation of the gating channel is shown in

Figure 13

At the top is a typical Region 1 waveform which exhibits

shouldering on the lowest frequency and is almost sinusoi-

dal on the highest frequency In this example this waveform

is fed to both the timing and the gating channel The hyster-

esis level (of about 25%) has been drawn on this waveform

The second waveform is the output of the differentiator and

its bi-directional one shot This is the waveform on the Time

Pulse Out pin While there is a positive edge pulse at each

peak there is also noise at the shoulders In this example

the Time Pulse Out is connected directly to the Time Pulse

In without any external delay This output is therefore the

clock for the D flip-flop

The third waveform in

Figure 13 is the output of the Compar-

ator with Hysteresis which goes to the D input of the flip-

flop The true peaks are the first positive edges of the Time

Pulse Out which occur after the output of the comparator

has changed states The D flip-flop will ‘‘clock’’ in these

valid peaks to the output bi-directional one shot Therefore

the noise pulses (due to the differentiator responding to

noise at the baseline) just ‘‘clock’’ in the old data through

the flip-flop and the output does not change

The Q output of the flip-flop drives the output bidirectional

one-shot which generates the positive edges corresponding

to the peaks The width of the data pulses can be controlled

by an external capacitor from the Set Pulse Width pin to

ground This pulse width can be adjusted from 20 ns to

the period of the highest frequency Typical values for this

capacitor are 20 pF for a 25 ns pulse width to 100 pF for a

100 ns pulse

TLF5283 – 19

FIGURE 13 Time and Gate Channel Operation for Region 1 Signals

DP8464B Datasheet(PDF) 15 Page - National Semiconductor (TI)

DP8464B Datasheet(HTML) 15 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL