LM3753 datasheet(34/49 Pages) TI1

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öC = 2 x S x fC

öSW = 2 x S x fSW

öZ =

CO x RC

öP =

L x CO

Ri = A x RS

T =

fSW

D =

VIN

Km =

(0.5 ± D) x Ri x

+ KFF

RFBT = RFBB x

VOUT

VREF

- 1

LM3753

SNVS614B – DECEMBER 2009 – REVISED MARCH 2013

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Control Loop Design Procedure

Once the power stage design is complete, the power stage components are used to determine the proper

frequency compensation. Knowing the dc modulator gain and assuming an ideal single-pole system response,

the mid-band error amplifier gain is set by the target crossover frequency. Based on the ideal amplifier transfer

function, the zero-pair is set to cancel the complex conjugate pole of the output filter. One pole is set to cancel

the ESR of the output capacitor. The second pole is set equal to the switching frequency. A correction factor is

used to accommodate the modulator damping when the output filter pole is within a decade of the target

crossover frequency.

The compensation components will scale from the feedback divider ratio and selection of the bottom feedback

divider resistor. A maximum value for the divider current is typically set at 1 mA. Using a divider current of 200

μA will allow for a reasonable range of values. For the bottom feedback resistor RFBB = VREF / 200 μA = 3 kΩ.

Choosing a standard 1% value of 3.01 k

Ω, the top feedback resistor is found from:

(64)

For VOUT = 1.2V and VREF = 0.6V, RFBT = 3.01 kΩ.

Based on the previously defined power stage values, calculate general terms:

(65)

For the design example D = 0.1, Ri = 0.026Ω, T = 3.33 μs and Km = 3.22.

Calculate the output filter pole frequency and the ESR zero frequency from:

(66)

For the output filter pole using CO = CO1 + CO2, ωP = 68.5 krad/sec. Since CO1 >> CO2, the ESR zero is

calculated using CO1 and RC1 as ωZ = 909 krad/sec.

Choose a target crossover frequency fC greater than the minimum control loop bandwidth from the OUTPUT

CAPACITORS section. The optimum value of the crossover frequency is usually between 5 and 10 times the

filter pole frequency. With fP = ωP / (2 x π) = 10.9 kHz, this places fC between 54.5 kHz and 109 kHz. The upper

limit for fC is typically set at 1/5 of the switching frequency.

(67)

Choosing fC = 60 kHz for the design example ωC = 377 krad/sec. The switching frequency is ωSW = 1.88

Mrad/sec.

For output capacitors with very low ESR, if the target crossover frequency is more than 10 times the filter pole

frequency, bandwidth limiting of the error amplifier may occur. See the Comprehensive Equations section to

incorporate the error amplifier bandwidth into the design procedure.

For reference, the parallel equivalent CO and RC at any frequency can be calculated from:

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