PC16550D

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SNLS378C – JUNE 1995 – REVISED MAY 2015

Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was

not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby

destroying the previous character. The OE indicator is set to a logic 1 upon detection of an overrun condition and

reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to fill

the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next character

has been completely received in the shift register. OE is indicated to the CPU as soon as it happens. The

character in the shift register is overwritten, but it is not transferred to the FIFO.

Bit 2: This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have the

correct even or odd parity, as selected by the even-parityselect bit. The PE bit is set to a logic 1 upon detection

of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line Status Register. In the

FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is revealed to

the CPU when its associated character is at the top of the FIFO.

Bit 3: This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a valid

Stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is detected as a logic

0 bit (Spacing level). The FE indicator is reset whenever the CPU reads the contents of the Line Status Register.

In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is

revealed to the CPU when its associated character is at the top of the FIFO. The UART will try to resynchronize

after a framing error. To do this it assumes that the framing error was due to the next start bit, so it samples this

‘‘start’’ bit twice and then takes in the ‘‘data’’.

Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is

held in the Spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit +

data bits + Parity + Stop bits). The BI indicator is reset whenever the CPU reads the contents of the Line Status

Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This

error is revealed to the CPU when its associated character is at the top of the FIFO. When break occurs only one

zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state

and receives the next valid start bit.

NOTE

Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt

whenever any of the corresponding conditions are detected and the interrupt is enabled.

Table 5. Interrupt Control Functions

FIFO

Interrupt

Mode

Identification

Interrupt Set and Reset Functions

Only

Register

Priority

Bit 3

Bit 2 Bit 1

Bit 0

Interrupt Type

Interrupt Source

Interrupt Reset Control

Level

0

0

0

1

–

None

None

–

0

1

1

0

Highest

Receiver Line

Overrun Error or Parity Error or

Reading the Line Status Register

Status

Framing Error or Break Interrupt

0

1

0

0

Second

Received Data

Receiver Data Available or Trigger

Reading the Receiver Buffer Register

Available

Level Reached

or the FIFO Drops Below the Trigger

Level

1

1

0

0

Second

Character Timeout

No Characters Have Been

Reading the Receiver

Indication

Removed From or Input to the

RCVR FIFO During the Last 4

Char. Times and There Is at Least

1 Char. in It During This Time

0

0

1

0

Third

Transmitter

Transmitter Holding Register Empty

Reading the IIR Register (if source of

Holding Register

interrupt) or Writing into the

Empty

Transmitter Holding Register

0

0

0

0

Fourth

MODEM Status

Clear to Send or Data Set Ready or Reading the MODEM Status Register

Ring Indicator or Data Carrier

Detect

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