PC16550DN datasheet(8/33 Pages) TI1

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PC16550D

SNLS378C – JUNE 1995 – REVISED MAY 2015

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

All input or output voltages with respect to VSS

–0.5

Power Dissipation

Storage temperature, Tstg

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

V(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

±1500

C101(2)

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Ambient Temperature

°C

VDD

Supply Voltage

4.5

5.5

7.4 Electrical Characteristics

TA = 0°C to 70°C, VDD = 5 V ± 10%, VSS = 0 V, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VILX

Clock input low voltage

–0.5

0.8

VIHX

Clock input high voltage

2.0

VDD

VIL

Input low voltage

–0.5

0.8

VIH

Input high voltage

VDD

VOL

Output low voltage

IOL = 1.6 mA on all

(1)

0.4

VOH

Output high voltage

IOH = –1.0 mA

(1)

2.4

VDD = 5.5 V, TA = 25°C, No Loads on output,

ICC(AV)

Average power supply current

SIN, DSR, DCD, CTS, RI = 2.0 V,

All other inputs = 0.8 V

IIL

Input leakage

±10

VDD = 5.5 V, VSS = 0 V, All other pins floating,

VIN = 0 V, 5.5 V

ICL

Clock leakage

±10

VDD = 5.5 V, VSS = 0 V, VOUT = 0 V, 5.25 V

IOZ

TRI-STATE leakage

1) Chip deselected

±20

2) WRITE mode, chip selected

VILMR

MR Schmitt VIL

0.8

VIHMR

MR Schmitt VIH

CAPACITANCE: TA = 25°C, VDD = VSS = 0 V

CXIN

Clock input capacitance

CXOUT

Clock output capacitance

CIN

Input capacitance

fc = 1 MHz, Unmeasured pins returned to VSS

COUT

Output capacitance

CI/O

Input/Output capacitance

(1)

Does not apply to XOUT.

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