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PC16550DN Datasheet(PDF) 9 Page - Texas Instruments |
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PC16550DN Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 33 page  PC16550D www.ti.com SNLS378C – JUNE 1995 – REVISED MAY 2015 7.5 Timing Requirements TA = 0°C to 70C, VDD = 5 V ± 10% MIN MAX UNIT tADS Address strobe width 60 ns tAH Address hold time 0 ns tAR RD, RD delay from address See (1) 30 ns tAS Address setup time 60 ns tAW WR, WR delay from address See (1) 30 ns tCH Chip select hold time 0 ns tCS Chip select setup time 60 ns tCSR RD, RD delay from chip select See (1) 30 ns tCSW WR, WR delay from select See (1) 30 ns tDH Data hold time 30 ns tDS Data setup time 30 ns tHZ RD, RD to floating data delay At 100 pF loading (2) 0 100 ns tMR Master reset pulse width 5000 ns tRA Address hold time from RD, RD See (1) 20 ns tRC Read cycle delay 125 ns tRCS Chip select hold time from RD, RD See (1) 20 ns tRD RD, RD strobe width 125 ns tRDD RD, RD to driver enable/disable At 100 pF loading (2) 60 ns tRVD Delay from RD, RD to data At 100 pF loading 60 ns tWA Address hold time from WR, WR See (1) 20 ns tWC Write cycle delay 150 ns tWCS Chip select hold time from WR, WR See (1) 20 ns tWR WR, WR strobe width 100 ns tXH Duration of clock high pulse External Clock (8, Max.) 55 ns tXL Duration of clock low pulse External Clock (8, Max.) 55 ns RC Read cycle = tAR + tRD + tRC 280 ns WC Write cycle = tAW + tWR + tWC 280 ns BAUD GENERATOR N Baud divisor 1 216–1 tBHD Baud output positive edge delay 100-pF Load 175 ns tBLD Baud output negative edge delay 100-pF Load 175 ns tHW Baud output up time fX = 8, ÷2, 100-pF Load 75 ns tLW Baud output down time fX = 8, ÷2, 100-pF Load 100 ns RECEIVER Delay from active edge of RD to Reset tRAI Interrupt – ns Delay from RD, RD (RD RBR/or RD LSR) to tRINT 100-pF Load 1000 ns Reset Interrupt tRXI Delay from RD RBR to RXRDY Inactive 290 ns tSCD Delay from RCLK to sample time 2000 ns RCLK tSINT Delay from Stop to Set Interrupt See (3) 1 Cycles (1) Applicable only when ADS is tied low. (2) Charge and discharge time is determined by VOL, VOH and the external loading. (3) In the FIFO mode (FCR0=1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs. Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: PC16550D |
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