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PCM1601 Datasheet(PDF) 5 Page - Texas Instruments |
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PCM1601 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 30 page ![]() ® 5 PCM1600, PCM1601 P I N NAME I / O DESCRIPTION 1 ZERO1 O Zero Data Flag for VOUT1. 2 ZERO2 O Zero Data Flag for VOUT2. 3 ZERO3 O Zero Data Flag for VOUT3. 4 ZERO4 O Zero Data Flag for VOUT4. 5 ZERO5 O Zero Data Flag for VOUT5. 6 ZERO6 O Zero Data Flag for VOUT6. 7 AGND — Analog Ground 8VCC — Analog Power Supply, +5V 9VOUT6 O Voltage Output of Audio Signal Corresponding to Rch on DATA3. 10 VOUT5 O Voltage Output of Audio Signal Corresponding to Lch on DATA3. 11 VOUT4 O Voltage Output of Audio Signal Corresponding to Rch on DATA2. 12 VOUT3 O Voltage Output of Audio Signal Corresponding to Lch on DATA2. 13 VOUT2 O Voltage Output of Audio Signal Corresponding to Rch on DATA1. 14 VOUT1 O Voltage Output of Audio Signal Corresponding to Lch on DATA1. 15 VCOM2 O Common Voltage Output. This pin should be bypassed with a 10 µF capacitor to AGND. 16 VCOM1 O Common Voltage Output. This pin should be bypassed with a 10 µF capacitor to AGND. 17 AGND6 — Analog Ground 18 VCC6 — Analog Power Supply, +5V 19 AGND5 — Analog Ground 20 VCC5 — Analog Power Supply, +5V 21 AGND4 — Analog Ground 22 VCC4 — Analog Power Supply, +5V 23 AGND3 — Analog Ground 24 VCC3 — Analog Power Supply, +5V 25 AGND2 — Analog Ground 26 VCC2 — Analog Power Supply, +5V 27 AGND1 — Analog Ground 28 VCC1 — Analog Power Supply, +5V 29 AGND0 — Analog Ground 30 VCC0 — Analog Power Supply, +5V 31 NC — No Connection. Must be open. 32 NC — No Connection. Must be open. 33 MDO O Serial Data Output for Function Register Control Port(3) 34 MDI I Serial Data Input for Function Register Control Port(1) 35 MC I Shift Clock for Function Register Control Port(1) 36 ML I Latch Enable for Function Register Control Port(1) 37 RST I System Reset, Active LOW(1) 38 SCLKI I System Clock In. Input frequency is 256, 384, 512 or 768fS.(2) 39 SCLKO O Buffered Clock Output. Output frequency is 256, 384, 512, or 768fS and one-half of 256, 384, 512, or 768fS. 40 BCK I Shift Clock Input for Serial Audio Data(2) 41 LRCK I Left and Right Clock Input. This clock is equal to the sampling rate, fS.(2) 42 TEST — Test Pin. This pin should be connected to DGND.(1) 43 VDD — Digital Power Supply, +3.3V 44 DGND — Digital Ground for +3.3V 45 DATA1 I Serial Audio Data Input for VOUT1 and VOUT2(2) 46 DATA2 I Serial Audio Data Input for VOUT3 and VOUT4(2) 47 DATA3 I Serial Audio Data Input for VOUT5 and VOUT6(2) 48 ZEROA I Zero Data Flag. Logical “AND” of ZERO1 through ZERO6. NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output. PIN ASSIGNMENTS |
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