PCM1601 datasheet(12/30 Pages) TI1

12 / 30 page

PCM1600, PCM1601

All Write operations for the serial control port use 16-bit

data words. Figure 6 shows the control data word format.

The most significant bit is the Read/Write (R/W) bit. When

set to ‘0’, this bit indicates a Write operation. There are

seven bits, labeled IDX[6:0], that set the register index (or

address) for the Write operation. The least significant eight

bits, D[7:0], contain the data to be written to the register

specified by IDX[6:0].

Figure 7 shows the functional timing diagram for writing the

serial control port. ML is held at a logic ‘1’ state until a

ML is set to logic ‘0’. Sixteen clocks are then provided on

MC, corresponding to the 16-bits of the control data word on

MDI. After the sixteenth clock cycle has completed, ML is

set to logic ‘1’ to latch the data into the indexed mode

control register.

IDX5

IDX6

R/W

IDX4

IDX2

IDX3

IDX1

IDX0

MSB

Read/Write Operation

0 = Write Operation

1 = Read Operation (register index is ignored)

LSB

FIGURE 6. Control Data Word Format for MDI.

FIGURE 7. Write Operation Timing.

SINGLE REGISTER READ OPERATION

Read operations utilize the 16-bit control word format shown

in Figure 6. For Read operations, the Read/Write (R/W) bit

is set to ‘1’. Read operations ignore the index bits, IDX[6:0],

of the control data word. Instead, the REG[6:0] bits in

Control Register 11 are used to set the index of the register

that is to be read during the Read operation. Bits IDX[6:0]

should be set to 00H for Read operations.

Figure 8 details the Read operation. First, Control Register

11 must be written with the index of the register to be read

back. Additionally, the INC bit must be set to logic ‘0’ in

order to disable the Auto-Increment Read function. The

Read cycle is then initiated by setting ML to logic ‘0’ and

setting the R/W bit of the control data word to logic ‘1’,

indicating a Read operation. MDO remains at a high-imped-

ance state until the last 8 bits of the 16-bit read cycle, which

D15 D14

IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0

MDI

FIGURE 5. Audio Interface Timing.

SYMBOL

PARAMETER

MIN

MAX

UNITS

tBCY

BCK Pulse Cycle Time

48 or 64fS(1)

tBCH

BCK High Level Time

tBCL

BCK Low Level Time

tBL

BCK Rising Edge to LRCK Edge

tLB

LRCK Falling Edge to BCK Rising Edge

tDS

DIN Set Up Time

tDH

DIN Hold Time

NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)

LRCK

BCK

DATA1-DATA3

50% of V

BCH

BCL

BCY

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