LM96551

SNAS511B – OCTOBER 2011 – REVISED MAY 2013

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FUNCTIONAL DESCRIPTION

Note that the case, PINn = NNn = HI is not allowed as it will damage the output transistors.

Logic inputs

Output

EN

PINn

NINn

Voutn

1

0

0

0V

1

1

0

VPP - 0.7V

1

0

1

VNN + 0.7V

1

1

1

not allowed

0

X

X

0V

APPLICATIONS INFORMATION

POWER-UP AND POWER-DOWN SEQUENCES

VSUB must always be the most negative supply, i.e., it must be equal to or more negative than the most

negative supply, VNN or VDN.

Power UP Sequence:

1. Turn ON VSUB, hold EN pin LO

2. Turn On VLL

3. Turn ON VDD, VDN, VPP, and VNN

Power DOWN Sequence:

1. Turn OFF VDD, VDN, VPP & VNN

2. Turn OFF VLL

3. Turn OFF VSUB

10

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