SCL

SDA

START

REPEATED

START

STOP

START

30%

70%

30%

70%

MENB

30%

70%

LMP91000

SNAS506I – JANUARY 2011 – REVISED DECEMBER 2014

www.ti.com

6.7 Timing Requirements

Zero= 20% VREF.

(1)

MIN

TYP

MAX

UNIT

Clock Frequency

–40 to 80°C

10

100

kHz

Clock Low Time

–40 to 80°C

4.7

µs

Clock High Time

–40 to 80°C

4.0

µs

After this period, the first clock

Data valid

4.0

µs

pulse is generated

Set-up time for a repeated START condition

–40 to 80°C

4.7

µs

–40 to 80°C

0

ns

Data Set-up time

–40 to 80°C

250

ns

IL

≤ 3 mA;

CL

≤ 400 pF

250

ns

–40 to 80°C

Set-up time for STOP condition

–40 to 80°C

4.0

µs

Bus free time between a STOP and START

–40 to 80°C

4.7

µs

condition

Data valid time

–40 to 80°C

3.45

µs

Data valid acknowledge time

–40 to 80°C

3.45

µs

Pulse width of spikes that must be

–40 to 80°C

50

ns

t_timeout

SCL and SDA Timeout

–40 to 80°C

25

100

ms

–40 to 80°C

600

ns

–40 to 80°C

600

ns

–40 to 80°C

600

ns

enabling and disabling

(1)

Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

(2)

LMP91000 provides an internal 300-ns minimum hold time to bridge the undefined region of the falling edge of SCL.

(3)

This parameter is specified by design or characterization.

Figure 1. Timing Diagram

8

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