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P

D +

T

MAX

–T

A

q

JA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

−40

−20

0

20

40

60

80

100

G029

DGN Package

2 oz. Trace And Copper Pad

With Solder

DGN Package

2 oz. Trace And

Copper Pad

Without Solder

SOIC Package

High-K Test PCB

SOIC Package

Low-K Test PCB

THS4021

THS4022

SLOS265C – SEPTEMBER 1999 – REVISED JULY 2007

7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8. With these preparatory steps in place, the THS402xDGN IC is simply placed in position and run through the

solder reflow operation as any standard surface-mount component. This results in a part that is properly

installed.

The actual thermal performance achieved with the THS402xDGN in its PowerPAD package depends on the

application. In the example above, if the size of the internal ground plane is approximately 3 inches

× 3 inches

(7.62 cm

× 7.62 cm), then the expected thermal coefficient, θ

non-PowerPAD version of the THS402x IC (SOIC) is shown. For a given

shown in Figure 39 and is calculated by the following formula:

where:

MAXIMUM POWER DISSIPATION

vs

FREE-AIR TEMPERATURE

NOTE: Results are with no air flow and PCB size = 3 in.

× 3 in. (7.62 cm × 7.62 cm).

Figure 39. Maximum Power Dissipation vs Free-Air Temperature

More-complete details of the thermal pad installation process and thermal management techniques can be found

in the PowerPAD Thermally Enhanced Package application report (SLMA002).

16

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Product Folder Link(s): THS4021 THS4022