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R1 output

G1 output

B1 output

R1SW bit

G1SW bit

B1SW bit

10% 10%

20%

40%

10%

OFF ON

EN_BLINK bit

R1, G1, B1

CYCLE EN bits

100 - 10 - 10 = 80%

OFF

100 - 20 - 20 = 60%

100 - 40 - 10 = 50%

10% 10%

OFF ON

20%

OFF

Blinking cycle time

Remaining OFF time

LP3952

www.ti.com

SNVS518A – JULY 2007 – REVISED MARCH 2013

Blinking ON/OFF cycle is defined so that there will be first OFF-period then ON-period after which follows an off-

period for the remaining cycle time that can not be set. If OFF and ON times are together more than 100% the

first OFF time will be as set and the ON time is cut to meet 100%. For example, if 50% OFF time is set and ON

time is set greater than 50%, only 50% ON time is used, the exceeding ON time is ignored. If OFF and ON times

are together less than 100% the remaining cycle time output is OFF.

Values for setting the blinking cycle for RGB1 can be seen in following table:

Table 3. R1, G1 and B1 Cycle Registers (02H, 04H and 06H):(1.65V

≤ VDDIO ≤ VDD1,2V) (unless otherwise

noted)

Name

Bit

Decription

R1_CYCLE_EN

Blinking enable

G1_CYCLE_EN

0 = disabled

B1_CYCLE_EN

1 = enabled, output state is defined with blinking cycle

R1_CYCLE[2:0]

2-0

RGB1 cycle time

G1_CYCLE[2:0]

Bits

Blinking cycle time

Blinking frequency

B1_CYCLE[2:0]

000

0.1s

10 Hz

001

0.25s

4 Hz

010

0.5s

2 Hz

011

1 Hz

100

0.5 Hz

101

0.33 Hz

110

0.25 Hz

111

0.2 Hz

Table 4. PATTERN_GEN_CTRL Register (11H):(1.65V

≤ VDDIO ≤ VDD1,2V) (unless otherwise noted)

Name

Bit

Description

EN_BLINK

Blinking sequence start bit

0 = disabled

1 = enabled

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