6

HV528

Functional Block Diagram

Level

Translator

16-bit

Latch

Logic

16-bit

Shift

Register

Logic

Level

Translator

Level

Translator

&

Buffer

VDD

DIN

CLK

DOUT

GND

GND

HVGND

HVGND

HVGND

HVGND

GND

BP

LE

POL

Function Table

Function

Inputs

Outputs

DIN

CLK

LE

POL

Shift Reg

1 2...16

HV Outputs

1 2...16

BP

DOUT

Load S/R

H OR L

↑

H

X

H or L ●...●

● ●...●

X

●

Transfer data in

latch

X

L

L

H

* *..........*

* *..........*

L

●

X

L

L

L

* *..........*

* *..........*

(b)

H

●

Store data in latches

X

X

H

H

● ●...●

● ●...●

L

●

X

X

H

L

● ●...●

● ●...●

(b)

H

●

Transparent mode

L

↑

L

H

L ●...●

L ●...●

L

●

H

↑

L

H

H ●...●

H ●...●

L

●

Invert mode

X

X

H

L

● ●...●

● ●...●

(b)

H

X

X

X

H

H

● ●...●

● ●...●

L

X

Notes:

H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition

● = dependent on previous stage’s state before the last CLK or last LE low

* = data at the last CLK ↑

(b) = bar over all symbols