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2:1

MUX

PRBS

Generator

10 Bit

Registers

TD(0-9)

PRBSEN

LOOPEN

Parallel to

Serial

Phase Generator

Clock

REFCLK

Control

Logic

MODESEL

ENABLE

TESTEN

Interpolator

and

Clock Extraction

PRBS

Verification

Serial to Parallel

and

Comma Detect

Clock

RBC1

RBC0

SYNC/PASS

RD(0-9)

SYNCEN

RBCMODE

JTAG

Control

Register

JTMS

JTRSTN

JTDI

TCK

JTDO

2:1

MUX

2:1

MUX

Clock

Data

TXP

TXN

RXP

RXN

LOS

TLK2201

TLK2201I

ETHERNET TRANSCEIVERS

SLLS420F – JUNE 2000 – REVISED SEPTEMBER 2007

Block Diagram

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Signal

TXP TXN

62 61

PECL

Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or

O

an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and

are active when LOOPEN is low.

RXP RXN

54 52

PECL I

Differential input receive. RXP and RXN together are the differential serial input interface from a

copper or an optical I/F module.

REFCLK

22

I

Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter

interface (100 MHz to 160 MHz). The transmitter uses this clock to register the input data (TD0-TD9)

for serialization. In the TBI mode that data is registered on the rising edge of REFCLK. In the DDR

mode, the data is registered on both the rising and falling edges of REFCLK with the most significant

bits aligned to the rising edge of REFCLK.

TD0-TD9

2-4, 6-9,

I

Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data

11-13

output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel

data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream

with TD0 sent as the first bit. When in the DDR mode (MODESEL = high) only TD0-TD4 are valid.

The 5-bit parallel data is clocked into the transceiver on the rising and falling edge of REFCLK and

transmitted as a serial stream with TD0 sent as the first bit.

RD0-RD9

45, 44, 43,

O

Receive data. When in TBI mode (MODESEL = low) these outputs carry 10-bit parallel data output

41, 40, 39,

from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1,

38, 36, 35,

depending on the receive clock mode selected. RD0 is the first bit received. When in the DDR mode

34

(MODESEL = high) only RD0-RD4 are valid. RD5-RD9 are held low. The 5-bit parallel data is

clocked out of the transceiver on the rising edge of RBC0.

Copyright © 2000–2007, Texas Instruments Incorporated

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