www.ti.com

DETAILED DESCRIPTION

Data Transmission

Transmission Latency

10 Bit Code

TXP, TXN

TD(0-9)

REFCLK

10 Bit Code

b9

Data Reception

TLK2201

TLK2201I

ETHERNET TRANSCEIVERS

SLLS420F – JUNE 2000 – REVISED SEPTEMBER 2007

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

VDDPLL

18

Supply

PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

GROUND

GNDA

51,58

Ground

Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.

GND

1, 14,

Ground

Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.

21,25, 33,

46

GNDPLL

64

Ground

PLL ground. Provides a ground for the PLL circuitry.

These devices support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR

clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is

selected.

In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,

TD0-TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock

by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted

sequentially bit 0 through 9 over the differential high-speed I/O channel.

In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0-TD4. In this mode data is

aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and sent

to the serializer. The rising edge REFCLK clocks in bit 0-4, and the falling edge of REFCLK clocks in bits 5-9. (

Bit 0 is the first bit transmitted).

Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit

9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The

minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times.

Figure 1. Transmitter Latency Full Rate Mode

The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated

clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and

presented to the protocol controller along with receive byte clocks (RBC0, RBC1).

Copyright © 2000–2007, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): TLK2201 TLK2201I