MIC4690

Micrel

MIC4690

10

June 2001

SW

L1

VIN

FB

GND

SHDN

R2

D1

MIC4690BM

GND

+4V to +30V

(34V transients)

Power

SOP-8

5678

4

3

2

1

Figure 5. Critical Traces for Layout

SW

L1

18µH

IN

FB

GND

SHDN

D1

2A

40V

J2

1A

J4

GND

U1 MIC4690BM

C2

0.1µF

50V

C1

22µF

35V

J1

4V to +30V

(34V transients)

J3

GND

SOP-8

5Ð8

4

3

2

1

JP1

ON

OFF

C4

220µF

10V

C3* 1800pF / 50V

optional

C5

0.1µF

50V

R1

3.01k

R2

6.49k

JP2a

1.8V

R6

optional

R3

2.94k

R4

1.78k

R5

976½

JP2b

2.5V

JP2c

3.3V

JP2d

5.0V

1

2

3

4

5

6

7

8

* C3 can be used to provide additional stability

and improved transient response.

Figure 6a. Evaluation Board Schematic Diagram

To minimize stray inductance and ground loops, keep trace

lengths, indicated by the heavy lines in Figure 5, as short as

possible. For example, keep D1 close to pin 3 and pins 5

through 8, keep L1 away from sensitive node FB, and keep

C

Information: Thermal Considerations” for ground plane lay-

out.

The feedback pin should be kept as far way from the switching

elements (usually L1 and D1) as possible.

A circuit with sample layouts are provided. See Figures 6a

though 6e. Gerber files are available upon request.