AD7490BCP datasheet(12/24 Pages) AD

12 / 24 page

–12–

AD7490

REV. A

Figure 4 shows how a sequence of consecutive channels can be

converted on without having to program the Shadow Register or

write to the part on each serial transfer. Again, to exit this mode of

operation and revert back to the normal mode of operation of a

multichannel ADC (as outlined in Figure 2), ensure the WRITE

Bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer.

POWER ON

DUMMY CONVERSIONS

DIN = ALL 1s

DIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1,

SELECT CODING, RANGE, AND POWER MODE

SELECT CHANNEL A3–A0 FOR CONVERSION,

SEQ = 1 SHADOW = 1

DOUT: CONVERSION RESULT FROM CHANNEL 0

CONTINUOUSLY CONVERTS ON A CONSECUTIVE

SEQUENCE OF CHANNELS FROM CHANNEL 0 UP

TO AND INCLUDING THE PREVIOUSLY SELECTED

A3–A0 IN THE CONTROL REGISTER

WRITE BIT = 0

CONTINUOUSLY CONVERTS ON THE SELECTED

SEQUENCE OF CHANNELS BUT WILL ALLOW

RANGE, CODING, AND SO ON, TO CHANGE IN THE

CONTROL REGISTER WITHOUT INTERRUPTING

THE SEQUENCE PROVIDED, SEQ = 1, SHADOW = 0

WRITE BIT = 1,

SEQ = 1,

SHADOW = 0

WRITE BIT = 1,

SEQ = 1,

SHADOW = 0

Figure 4. SEQ Bit = 1, SHADOW Bit = 1 Flowchart

CIRCUIT INFORMATION

The AD7490 is a fast, 16-channel, 12-bit, single-supply, A/D conver-

ter. The parts can be operated from a 2.7 V to 5.25 V supply. When

operated from a 5 V supply, the AD7490 is capable of throughput

rates of up to 1 MSPS when provided with a 20 MHz clock.

The AD7490 provides the user with an on-chip track/hold, A/D

converter, and a serial interface housed in either 28-lead TSSOP or

32-lead LFCSP package. The AD7490 has 16 single-ended

input channels with a channel sequencer, allowing the user to select

a sequence of channels through which the ADC can cycle with

each consecutive

CS falling edge. The serial clock input accesses

data from the part, controls the transfer of data written to the ADC,

and provides the clock source for the successive-approximation

A/D converter. The analog input range for the AD74790 is 0 to

REFIN or 0 to 2

REFIN depending on the status of Bit 1 in the

Control Register. For the 0 to 2

REFIN range, the part must

be operated from a 4.75 V to 5.25 V supply.

The AD7490 provides flexible power management options to

allow the user to achieve the best power performance for a given

throughput rate. These options are selected by programming the

Power Management bits in the Control Register.

CONVERTER OPERATION

The AD7490 is a 12-bit successive approximation analog-to-digital

converter based around a capacitive DAC. The AD7490 can convert

analog input signals in the range 0 V to VREF IN or 0 V to 2

VREF IN.

Figures 5 and 6 show simplified schematics of the ADC. The ADC

comprises Control Logic, SAR, and a Capacitive DAC, which are

used to add and subtract fixed amounts of charge from the sampling

capacitor to bring the comparator back into a balanced condition.

Figure 5 shows the ADC during its acquisition phase. SW2 is closed

and SW1 is in position A. The comparator is held in a balanced

condition and the sampling capacitor acquires the signal on the

selected VIN channel.

VIN0

VIN15

AGND

SW1

SW2

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 5. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 6), SW2 will

open and SW1 will move to position B causing the comparator

to become unbalanced. The Control Logic and the Capacitive

DAC are used to add and subtract fixed amounts of charge from

the sampling capacitor to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion is

complete. The Control Logic generates the ADC output code.

Figure 8 shows the ADC transfer function.

VIN0

VIN15

AGND

SW1

SW2

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

Figure 6. ADC Conversion Phase

Analog Input

Figure 7 shows an equivalent circuit of the analog input structure

of the AD7490. The two diodes, D1 and D2, provide ESD pro-

tection for the analog inputs. Care must be taken to ensure that

the analog input signal never exceeds the supply rails by more

than 200 mV. This will cause these diodes to become forward

biased and start conducting current into the substrate. 10 mA is the

maximum current these diodes can conduct without causing

irreversible damage to the part. The capacitor C1 in Figure 7 is

typically about 4 pF and can primarily be attributed to pin

capacitance. The resistor R1 is a lumped component made up of

VIN

4pF

30pF

VDD

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

Figure 7. Equivalent Analog Input Circuit

AD7490BCP Datasheet(PDF) 12 Page - Analog Devices

AD7490BCP Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL