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INA260

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SBOS656A – JULY 2016 – REVISED AUGUST 2016

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Table 13. Mask/Enable Register (06h) (Read/Write)

BIT #

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BIT

NAME

OCL

UCL

BOL

BUL

POL

CNVR

—

—

—

—

—

AFF

CVRF

OVF

APOL

LEN

POR

VALUE

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

OCL:

Over Current Limit (Read/Write)

Bit 15

Setting this bit high configures the Alert pin to be asserted if the current measurement following a conversion

exceeds the value programmed in the Alert Limit Register.

UCL:

Under Current Limit (Read/Write)

Bit 14

Setting this bit high configures the Alert pin to be asserted if the current measurement following a conversion drops

below the value programmed in the Alert Limit Register.

BOL:

Bus Voltage Over-Voltage (Read/Write)

Bit 13

Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion

exceeds the value programmed in the Alert Limit Register.

BUL:

Bus Voltage Under-Voltage (Read/Write)

Bit 12

Setting this bit high configures the Alert pin to be asserted if the bus voltage measurement following a conversion

drops below the value programmed in the Alert Limit Register.

POL:

Power Over-Limit (Read/Write)

Bit 11

Setting this bit high configures the Alert pin to be asserted if the Power calculation made following a bus voltage

measurement exceeds the value programmed in the Alert Limit Register.

CNVR:

Conversion Ready (Read/Write)

Bit 10

Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag, Bit 3, is asserted

indicating that the device is ready for the next conversion.

AFF:

Alert Function Flag (Read-Only)

Bit 4

While only one Alert Function can be monitored at the Alert pin at a time, the Conversion Ready can also be

enabled to assert the Alert pin. Reading the Alert Function Flag following an alert allows the user to determine if the

Alert Function was the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit clears only when the Mask/Enable

Register is read. When the Alert Latch Enable bit is set to Transparent mode, the Alert Function Flag bit is cleared

following the next conversion that does not result in an Alert condition.

CVRF:

Conversion Ready Flag (Read-Only)

Bit 3

Although the device can be read at any time, and the data from the last conversion is available, the Conversion

Ready Flag bit is provided to help coordinate one-shot or triggered conversions. The Conversion Ready Flag bit is

set after all conversions, averaging, and multiplications are complete. Conversion Ready Flag bit clears under the

following conditions:

1.) Writing to the Configuration Register (except for Power-Down selection)

2.) Reading the Mask/Enable Register

OVF:

Math Overflow Flag (Read-Only)

Bit 2

This bit is set to '1' if an arithmetic operation resulted in an overflow error. It indicates that current and power data

may be invalid.

APOL:

Alert Polarity bit (Read/Write)

Bit 1

1 = Inverted (active-high open collector)

0 = Normal (active-low open collector) (default)