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INA260

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SBOS656A – JULY 2016 – REVISED AUGUST 2016

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8.5 Programming

8.5.1 Calculating Returned Values

The LSB size for the Bus Voltage Register (02h), Current Register, and Power Register are fixed and are shown

in Table 1. To calculate any of the values for current, voltage or power take the decimal value returned by the

device and multiply that value by the LSB size. For example, the LSB for the bus voltage is 1.25 mV/bit, if the

device returns a decimal value of 9584 (2570h), the value of the bus voltage is calculated to be 1.25mV x 9584 =

11.98V.

REGISTER NAME

ADDRESS

CONTENTS

DEC

LSB

VALUE

Bus Voltage Register

02h

2570h

9584

1.25 mV

11.98 V

Current Register

04h

2710

10000

1.25 mA

12.5 A

Power Register

03h

3A7Fh

14975

10 mW

149.75 W

8.5.2 Default Settings

The default power-up states of the registers are shown in the Register Maps section of this data sheet. These

registers are volatile, and if programmed to a value other than the default values shown in Table 4, they must be

re-programmed at every device power-up.

8.5.3 Bus Overview

essentially compatible with one another.

when a difference between the two systems is discussed. Two lines, SCL and SDA, connect the device to the

bus. Both SCL and SDA connect to the bus and require external pull-up resistors.

The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.

The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,

and generates START and STOP conditions.

To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

start or stop condition.

After all data have been transferred, the master generates a stop condition, indicated by pulling SDA from low to

high while SCL is high. The device includes a 28 ms timeout on its interface to prevent locking up the bus.