ATS128 datasheet(10/25 Pages) ALLEGRO

10 / 25 page

Highly Programmable, Back-Biased,

Hall-Effect Switch with TPOS Functionality

ATS128LSE

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Application Information

Figure 4. Typical Application Circuit

Figure 5. Concept of Chopper Stabilization Technique

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small signal voltage developed across

the Hall element. This voltage is disproportionally small relative

to the offset that can be produced at the output of the Hall sensor

IC. This makes it difficult to process the signal while maintain-

ing an accurate, reliable output over the specified operating

temperature and voltage ranges. Chopper stabilization is a unique

approach used to minimize Hall offset on the chip. Allegro

employs a patented technique to remove key sources of the out-

put drift induced by thermal and mechanical stresses. This offset

reduction technique is based on a signal modulation-demodula-

tion process. The undesired offset signal is separated from the

magnetic field-induced signal in the frequency domain, through

modulation. The subsequent demodulation acts as a modulation

process for the offset, causing the magnetic field-induced signal

to recover its original spectrum at base band, while the DC offset

becomes a high-frequency signal. The magnetic-sourced signal

then can pass through a low-pass filter, while the modulated DC

offset is suppressed. In addition to the removal of the thermal and

stress related offset, this novel technique also reduces the amount

of thermal noise in the Hall sensor IC while completely removing

the modulated residue resulting from the chopper operation. The

chopper stabilization technique uses a high frequency sampling

clock. For demodulation process, a sample and hold technique is

used. This high-frequency operation allows a greater sampling

rate, which results in higher accuracy and faster signal-processing

capability. This approach desensitizes the chip to the effects

of thermal and mechanical stresses, and produces devices that

have extremely stable quiescent Hall output voltages and precise

recoverability after temperature cycling. This technique is made

possible through the use of a BiCMOS process, which allows the

use of low-offset, low-noise amplifiers in combination with high-

density logic integration and sample-and-hold circuits.

Amp

Regulator

Clock/Logic

Hall Element

Tuned

Filter

Anit-aliasing

LP Filter

VCC

1.2 kΩ

100 Ω

V+

IC Output

GND

VOUT

CBYPASS

0.1 μF

120 pF

RLOAD

CLOAD

ATS128

Tie to device pins using

traces as short as possible

ATS128 Datasheet(PDF) 10 Page - Allegro MicroSystems

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